//megafunction wizard: %Altera SOPC Builder%
//GENERATION: STANDARD
//VERSION: WM1.0


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// synthesis translate_off
`timescale 1ns / 1ps
// synthesis translate_on

// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module Din_s1_arbitrator (
                           // inputs:
                            Din_s1_readdata,
                            clk,
                            cpu_data_master_address_to_slave,
                            cpu_data_master_read,
                            cpu_data_master_write,
                            reset_n,

                           // outputs:
                            Din_s1_address,
                            Din_s1_readdata_from_sa,
                            Din_s1_reset_n,
                            cpu_data_master_granted_Din_s1,
                            cpu_data_master_qualified_request_Din_s1,
                            cpu_data_master_read_data_valid_Din_s1,
                            cpu_data_master_requests_Din_s1,
                            d1_Din_s1_end_xfer
                         )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] Din_s1_address;
  output  [  7: 0] Din_s1_readdata_from_sa;
  output           Din_s1_reset_n;
  output           cpu_data_master_granted_Din_s1;
  output           cpu_data_master_qualified_request_Din_s1;
  output           cpu_data_master_read_data_valid_Din_s1;
  output           cpu_data_master_requests_Din_s1;
  output           d1_Din_s1_end_xfer;
  input   [  7: 0] Din_s1_readdata;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input            reset_n;

  wire    [  1: 0] Din_s1_address;
  wire             Din_s1_allgrants;
  wire             Din_s1_allow_new_arb_cycle;
  wire             Din_s1_any_bursting_master_saved_grant;
  wire             Din_s1_any_continuerequest;
  wire             Din_s1_arb_counter_enable;
  reg     [  2: 0] Din_s1_arb_share_counter;
  wire    [  2: 0] Din_s1_arb_share_counter_next_value;
  wire    [  2: 0] Din_s1_arb_share_set_values;
  wire             Din_s1_beginbursttransfer_internal;
  wire             Din_s1_begins_xfer;
  wire             Din_s1_end_xfer;
  wire             Din_s1_firsttransfer;
  wire             Din_s1_grant_vector;
  wire             Din_s1_in_a_read_cycle;
  wire             Din_s1_in_a_write_cycle;
  wire             Din_s1_master_qreq_vector;
  wire             Din_s1_non_bursting_master_requests;
  wire    [  7: 0] Din_s1_readdata_from_sa;
  reg              Din_s1_reg_firsttransfer;
  wire             Din_s1_reset_n;
  reg              Din_s1_slavearbiterlockenable;
  wire             Din_s1_slavearbiterlockenable2;
  wire             Din_s1_unreg_firsttransfer;
  wire             Din_s1_waits_for_read;
  wire             Din_s1_waits_for_write;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_Din_s1;
  wire             cpu_data_master_qualified_request_Din_s1;
  wire             cpu_data_master_read_data_valid_Din_s1;
  wire             cpu_data_master_requests_Din_s1;
  wire             cpu_data_master_saved_grant_Din_s1;
  reg              d1_Din_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_Din_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 23: 0] shifted_address_to_Din_s1_from_cpu_data_master;
  wire             wait_for_Din_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~Din_s1_end_xfer;
    end


  assign Din_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_Din_s1));
  //assign Din_s1_readdata_from_sa = Din_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign Din_s1_readdata_from_sa = Din_s1_readdata;

  assign cpu_data_master_requests_Din_s1 = (({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'h81060) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_read;
  //Din_s1_arb_share_counter set values, which is an e_mux
  assign Din_s1_arb_share_set_values = 1;

  //Din_s1_non_bursting_master_requests mux, which is an e_mux
  assign Din_s1_non_bursting_master_requests = cpu_data_master_requests_Din_s1;

  //Din_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign Din_s1_any_bursting_master_saved_grant = 0;

  //Din_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign Din_s1_arb_share_counter_next_value = Din_s1_firsttransfer ? (Din_s1_arb_share_set_values - 1) : |Din_s1_arb_share_counter ? (Din_s1_arb_share_counter - 1) : 0;

  //Din_s1_allgrants all slave grants, which is an e_mux
  assign Din_s1_allgrants = |Din_s1_grant_vector;

  //Din_s1_end_xfer assignment, which is an e_assign
  assign Din_s1_end_xfer = ~(Din_s1_waits_for_read | Din_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_Din_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_Din_s1 = Din_s1_end_xfer & (~Din_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //Din_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign Din_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_Din_s1 & Din_s1_allgrants) | (end_xfer_arb_share_counter_term_Din_s1 & ~Din_s1_non_bursting_master_requests);

  //Din_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Din_s1_arb_share_counter <= 0;
      else if (Din_s1_arb_counter_enable)
          Din_s1_arb_share_counter <= Din_s1_arb_share_counter_next_value;
    end


  //Din_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Din_s1_slavearbiterlockenable <= 0;
      else if ((|Din_s1_master_qreq_vector & end_xfer_arb_share_counter_term_Din_s1) | (end_xfer_arb_share_counter_term_Din_s1 & ~Din_s1_non_bursting_master_requests))
          Din_s1_slavearbiterlockenable <= |Din_s1_arb_share_counter_next_value;
    end


  //cpu/data_master Din/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = Din_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //Din_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign Din_s1_slavearbiterlockenable2 = |Din_s1_arb_share_counter_next_value;

  //cpu/data_master Din/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = Din_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //Din_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign Din_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_Din_s1 = cpu_data_master_requests_Din_s1;
  //master is always granted when requested
  assign cpu_data_master_granted_Din_s1 = cpu_data_master_qualified_request_Din_s1;

  //cpu/data_master saved-grant Din/s1, which is an e_assign
  assign cpu_data_master_saved_grant_Din_s1 = cpu_data_master_requests_Din_s1;

  //allow new arb cycle for Din/s1, which is an e_assign
  assign Din_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign Din_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign Din_s1_master_qreq_vector = 1;

  //Din_s1_reset_n assignment, which is an e_assign
  assign Din_s1_reset_n = reset_n;

  //Din_s1_firsttransfer first transaction, which is an e_assign
  assign Din_s1_firsttransfer = Din_s1_begins_xfer ? Din_s1_unreg_firsttransfer : Din_s1_reg_firsttransfer;

  //Din_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign Din_s1_unreg_firsttransfer = ~(Din_s1_slavearbiterlockenable & Din_s1_any_continuerequest);

  //Din_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Din_s1_reg_firsttransfer <= 1'b1;
      else if (Din_s1_begins_xfer)
          Din_s1_reg_firsttransfer <= Din_s1_unreg_firsttransfer;
    end


  //Din_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign Din_s1_beginbursttransfer_internal = Din_s1_begins_xfer;

  assign shifted_address_to_Din_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //Din_s1_address mux, which is an e_mux
  assign Din_s1_address = shifted_address_to_Din_s1_from_cpu_data_master >> 2;

  //d1_Din_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_Din_s1_end_xfer <= 1;
      else if (1)
          d1_Din_s1_end_xfer <= Din_s1_end_xfer;
    end


  //Din_s1_waits_for_read in a cycle, which is an e_mux
  assign Din_s1_waits_for_read = Din_s1_in_a_read_cycle & Din_s1_begins_xfer;

  //Din_s1_in_a_read_cycle assignment, which is an e_assign
  assign Din_s1_in_a_read_cycle = cpu_data_master_granted_Din_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = Din_s1_in_a_read_cycle;

  //Din_s1_waits_for_write in a cycle, which is an e_mux
  assign Din_s1_waits_for_write = Din_s1_in_a_write_cycle & 0;

  //Din_s1_in_a_write_cycle assignment, which is an e_assign
  assign Din_s1_in_a_write_cycle = cpu_data_master_granted_Din_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = Din_s1_in_a_write_cycle;

  assign wait_for_Din_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //Din/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module Dout_s1_arbitrator (
                            // inputs:
                             clk,
                             cpu_data_master_address_to_slave,
                             cpu_data_master_byteenable,
                             cpu_data_master_read,
                             cpu_data_master_waitrequest,
                             cpu_data_master_write,
                             cpu_data_master_writedata,
                             reset_n,

                            // outputs:
                             Dout_s1_address,
                             Dout_s1_chipselect,
                             Dout_s1_reset_n,
                             Dout_s1_write_n,
                             Dout_s1_writedata,
                             cpu_data_master_granted_Dout_s1,
                             cpu_data_master_qualified_request_Dout_s1,
                             cpu_data_master_read_data_valid_Dout_s1,
                             cpu_data_master_requests_Dout_s1,
                             d1_Dout_s1_end_xfer
                          )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] Dout_s1_address;
  output           Dout_s1_chipselect;
  output           Dout_s1_reset_n;
  output           Dout_s1_write_n;
  output  [  7: 0] Dout_s1_writedata;
  output           cpu_data_master_granted_Dout_s1;
  output           cpu_data_master_qualified_request_Dout_s1;
  output           cpu_data_master_read_data_valid_Dout_s1;
  output           cpu_data_master_requests_Dout_s1;
  output           d1_Dout_s1_end_xfer;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] Dout_s1_address;
  wire             Dout_s1_allgrants;
  wire             Dout_s1_allow_new_arb_cycle;
  wire             Dout_s1_any_bursting_master_saved_grant;
  wire             Dout_s1_any_continuerequest;
  wire             Dout_s1_arb_counter_enable;
  reg     [  2: 0] Dout_s1_arb_share_counter;
  wire    [  2: 0] Dout_s1_arb_share_counter_next_value;
  wire    [  2: 0] Dout_s1_arb_share_set_values;
  wire             Dout_s1_beginbursttransfer_internal;
  wire             Dout_s1_begins_xfer;
  wire             Dout_s1_chipselect;
  wire             Dout_s1_end_xfer;
  wire             Dout_s1_firsttransfer;
  wire             Dout_s1_grant_vector;
  wire             Dout_s1_in_a_read_cycle;
  wire             Dout_s1_in_a_write_cycle;
  wire             Dout_s1_master_qreq_vector;
  wire             Dout_s1_non_bursting_master_requests;
  wire             Dout_s1_pretend_byte_enable;
  reg              Dout_s1_reg_firsttransfer;
  wire             Dout_s1_reset_n;
  reg              Dout_s1_slavearbiterlockenable;
  wire             Dout_s1_slavearbiterlockenable2;
  wire             Dout_s1_unreg_firsttransfer;
  wire             Dout_s1_waits_for_read;
  wire             Dout_s1_waits_for_write;
  wire             Dout_s1_write_n;
  wire    [  7: 0] Dout_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_Dout_s1;
  wire             cpu_data_master_qualified_request_Dout_s1;
  wire             cpu_data_master_read_data_valid_Dout_s1;
  wire             cpu_data_master_requests_Dout_s1;
  wire             cpu_data_master_saved_grant_Dout_s1;
  reg              d1_Dout_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_Dout_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 23: 0] shifted_address_to_Dout_s1_from_cpu_data_master;
  wire             wait_for_Dout_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~Dout_s1_end_xfer;
    end


  assign Dout_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_Dout_s1));
  assign cpu_data_master_requests_Dout_s1 = (({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'h81070) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //Dout_s1_arb_share_counter set values, which is an e_mux
  assign Dout_s1_arb_share_set_values = 1;

  //Dout_s1_non_bursting_master_requests mux, which is an e_mux
  assign Dout_s1_non_bursting_master_requests = cpu_data_master_requests_Dout_s1;

  //Dout_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign Dout_s1_any_bursting_master_saved_grant = 0;

  //Dout_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign Dout_s1_arb_share_counter_next_value = Dout_s1_firsttransfer ? (Dout_s1_arb_share_set_values - 1) : |Dout_s1_arb_share_counter ? (Dout_s1_arb_share_counter - 1) : 0;

  //Dout_s1_allgrants all slave grants, which is an e_mux
  assign Dout_s1_allgrants = |Dout_s1_grant_vector;

  //Dout_s1_end_xfer assignment, which is an e_assign
  assign Dout_s1_end_xfer = ~(Dout_s1_waits_for_read | Dout_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_Dout_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_Dout_s1 = Dout_s1_end_xfer & (~Dout_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //Dout_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign Dout_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_Dout_s1 & Dout_s1_allgrants) | (end_xfer_arb_share_counter_term_Dout_s1 & ~Dout_s1_non_bursting_master_requests);

  //Dout_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Dout_s1_arb_share_counter <= 0;
      else if (Dout_s1_arb_counter_enable)
          Dout_s1_arb_share_counter <= Dout_s1_arb_share_counter_next_value;
    end


  //Dout_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Dout_s1_slavearbiterlockenable <= 0;
      else if ((|Dout_s1_master_qreq_vector & end_xfer_arb_share_counter_term_Dout_s1) | (end_xfer_arb_share_counter_term_Dout_s1 & ~Dout_s1_non_bursting_master_requests))
          Dout_s1_slavearbiterlockenable <= |Dout_s1_arb_share_counter_next_value;
    end


  //cpu/data_master Dout/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = Dout_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //Dout_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign Dout_s1_slavearbiterlockenable2 = |Dout_s1_arb_share_counter_next_value;

  //cpu/data_master Dout/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = Dout_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //Dout_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign Dout_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_Dout_s1 = cpu_data_master_requests_Dout_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //Dout_s1_writedata mux, which is an e_mux
  assign Dout_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_Dout_s1 = cpu_data_master_qualified_request_Dout_s1;

  //cpu/data_master saved-grant Dout/s1, which is an e_assign
  assign cpu_data_master_saved_grant_Dout_s1 = cpu_data_master_requests_Dout_s1;

  //allow new arb cycle for Dout/s1, which is an e_assign
  assign Dout_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign Dout_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign Dout_s1_master_qreq_vector = 1;

  //Dout_s1_reset_n assignment, which is an e_assign
  assign Dout_s1_reset_n = reset_n;

  assign Dout_s1_chipselect = cpu_data_master_granted_Dout_s1;
  //Dout_s1_firsttransfer first transaction, which is an e_assign
  assign Dout_s1_firsttransfer = Dout_s1_begins_xfer ? Dout_s1_unreg_firsttransfer : Dout_s1_reg_firsttransfer;

  //Dout_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign Dout_s1_unreg_firsttransfer = ~(Dout_s1_slavearbiterlockenable & Dout_s1_any_continuerequest);

  //Dout_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          Dout_s1_reg_firsttransfer <= 1'b1;
      else if (Dout_s1_begins_xfer)
          Dout_s1_reg_firsttransfer <= Dout_s1_unreg_firsttransfer;
    end


  //Dout_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign Dout_s1_beginbursttransfer_internal = Dout_s1_begins_xfer;

  //~Dout_s1_write_n assignment, which is an e_mux
  assign Dout_s1_write_n = ~(((cpu_data_master_granted_Dout_s1 & cpu_data_master_write)) & Dout_s1_pretend_byte_enable);

  assign shifted_address_to_Dout_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //Dout_s1_address mux, which is an e_mux
  assign Dout_s1_address = shifted_address_to_Dout_s1_from_cpu_data_master >> 2;

  //d1_Dout_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_Dout_s1_end_xfer <= 1;
      else if (1)
          d1_Dout_s1_end_xfer <= Dout_s1_end_xfer;
    end


  //Dout_s1_waits_for_read in a cycle, which is an e_mux
  assign Dout_s1_waits_for_read = Dout_s1_in_a_read_cycle & Dout_s1_begins_xfer;

  //Dout_s1_in_a_read_cycle assignment, which is an e_assign
  assign Dout_s1_in_a_read_cycle = cpu_data_master_granted_Dout_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = Dout_s1_in_a_read_cycle;

  //Dout_s1_waits_for_write in a cycle, which is an e_mux
  assign Dout_s1_waits_for_write = Dout_s1_in_a_write_cycle & 0;

  //Dout_s1_in_a_write_cycle assignment, which is an e_assign
  assign Dout_s1_in_a_write_cycle = cpu_data_master_granted_Dout_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = Dout_s1_in_a_write_cycle;

  assign wait_for_Dout_s1_counter = 0;
  //Dout_s1_pretend_byte_enable byte enable port mux, which is an e_mux
  assign Dout_s1_pretend_byte_enable = (cpu_data_master_granted_Dout_s1)? cpu_data_master_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //Dout/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module SEG_H_s1_arbitrator (
                             // inputs:
                              clk,
                              cpu_data_master_address_to_slave,
                              cpu_data_master_byteenable,
                              cpu_data_master_read,
                              cpu_data_master_waitrequest,
                              cpu_data_master_write,
                              cpu_data_master_writedata,
                              reset_n,

                             // outputs:
                              SEG_H_s1_address,
                              SEG_H_s1_chipselect,
                              SEG_H_s1_reset_n,
                              SEG_H_s1_write_n,
                              SEG_H_s1_writedata,
                              cpu_data_master_granted_SEG_H_s1,
                              cpu_data_master_qualified_request_SEG_H_s1,
                              cpu_data_master_read_data_valid_SEG_H_s1,
                              cpu_data_master_requests_SEG_H_s1,
                              d1_SEG_H_s1_end_xfer
                           )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] SEG_H_s1_address;
  output           SEG_H_s1_chipselect;
  output           SEG_H_s1_reset_n;
  output           SEG_H_s1_write_n;
  output  [  7: 0] SEG_H_s1_writedata;
  output           cpu_data_master_granted_SEG_H_s1;
  output           cpu_data_master_qualified_request_SEG_H_s1;
  output           cpu_data_master_read_data_valid_SEG_H_s1;
  output           cpu_data_master_requests_SEG_H_s1;
  output           d1_SEG_H_s1_end_xfer;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] SEG_H_s1_address;
  wire             SEG_H_s1_allgrants;
  wire             SEG_H_s1_allow_new_arb_cycle;
  wire             SEG_H_s1_any_bursting_master_saved_grant;
  wire             SEG_H_s1_any_continuerequest;
  wire             SEG_H_s1_arb_counter_enable;
  reg     [  2: 0] SEG_H_s1_arb_share_counter;
  wire    [  2: 0] SEG_H_s1_arb_share_counter_next_value;
  wire    [  2: 0] SEG_H_s1_arb_share_set_values;
  wire             SEG_H_s1_beginbursttransfer_internal;
  wire             SEG_H_s1_begins_xfer;
  wire             SEG_H_s1_chipselect;
  wire             SEG_H_s1_end_xfer;
  wire             SEG_H_s1_firsttransfer;
  wire             SEG_H_s1_grant_vector;
  wire             SEG_H_s1_in_a_read_cycle;
  wire             SEG_H_s1_in_a_write_cycle;
  wire             SEG_H_s1_master_qreq_vector;
  wire             SEG_H_s1_non_bursting_master_requests;
  wire             SEG_H_s1_pretend_byte_enable;
  reg              SEG_H_s1_reg_firsttransfer;
  wire             SEG_H_s1_reset_n;
  reg              SEG_H_s1_slavearbiterlockenable;
  wire             SEG_H_s1_slavearbiterlockenable2;
  wire             SEG_H_s1_unreg_firsttransfer;
  wire             SEG_H_s1_waits_for_read;
  wire             SEG_H_s1_waits_for_write;
  wire             SEG_H_s1_write_n;
  wire    [  7: 0] SEG_H_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_SEG_H_s1;
  wire             cpu_data_master_qualified_request_SEG_H_s1;
  wire             cpu_data_master_read_data_valid_SEG_H_s1;
  wire             cpu_data_master_requests_SEG_H_s1;
  wire             cpu_data_master_saved_grant_SEG_H_s1;
  reg              d1_SEG_H_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_SEG_H_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 23: 0] shifted_address_to_SEG_H_s1_from_cpu_data_master;
  wire             wait_for_SEG_H_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~SEG_H_s1_end_xfer;
    end


  assign SEG_H_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_SEG_H_s1));
  assign cpu_data_master_requests_SEG_H_s1 = (({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'h81090) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //SEG_H_s1_arb_share_counter set values, which is an e_mux
  assign SEG_H_s1_arb_share_set_values = 1;

  //SEG_H_s1_non_bursting_master_requests mux, which is an e_mux
  assign SEG_H_s1_non_bursting_master_requests = cpu_data_master_requests_SEG_H_s1;

  //SEG_H_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign SEG_H_s1_any_bursting_master_saved_grant = 0;

  //SEG_H_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign SEG_H_s1_arb_share_counter_next_value = SEG_H_s1_firsttransfer ? (SEG_H_s1_arb_share_set_values - 1) : |SEG_H_s1_arb_share_counter ? (SEG_H_s1_arb_share_counter - 1) : 0;

  //SEG_H_s1_allgrants all slave grants, which is an e_mux
  assign SEG_H_s1_allgrants = |SEG_H_s1_grant_vector;

  //SEG_H_s1_end_xfer assignment, which is an e_assign
  assign SEG_H_s1_end_xfer = ~(SEG_H_s1_waits_for_read | SEG_H_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_SEG_H_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_SEG_H_s1 = SEG_H_s1_end_xfer & (~SEG_H_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //SEG_H_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign SEG_H_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_SEG_H_s1 & SEG_H_s1_allgrants) | (end_xfer_arb_share_counter_term_SEG_H_s1 & ~SEG_H_s1_non_bursting_master_requests);

  //SEG_H_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SEG_H_s1_arb_share_counter <= 0;
      else if (SEG_H_s1_arb_counter_enable)
          SEG_H_s1_arb_share_counter <= SEG_H_s1_arb_share_counter_next_value;
    end


  //SEG_H_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SEG_H_s1_slavearbiterlockenable <= 0;
      else if ((|SEG_H_s1_master_qreq_vector & end_xfer_arb_share_counter_term_SEG_H_s1) | (end_xfer_arb_share_counter_term_SEG_H_s1 & ~SEG_H_s1_non_bursting_master_requests))
          SEG_H_s1_slavearbiterlockenable <= |SEG_H_s1_arb_share_counter_next_value;
    end


  //cpu/data_master SEG_H/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = SEG_H_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //SEG_H_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign SEG_H_s1_slavearbiterlockenable2 = |SEG_H_s1_arb_share_counter_next_value;

  //cpu/data_master SEG_H/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = SEG_H_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //SEG_H_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign SEG_H_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_SEG_H_s1 = cpu_data_master_requests_SEG_H_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //SEG_H_s1_writedata mux, which is an e_mux
  assign SEG_H_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_SEG_H_s1 = cpu_data_master_qualified_request_SEG_H_s1;

  //cpu/data_master saved-grant SEG_H/s1, which is an e_assign
  assign cpu_data_master_saved_grant_SEG_H_s1 = cpu_data_master_requests_SEG_H_s1;

  //allow new arb cycle for SEG_H/s1, which is an e_assign
  assign SEG_H_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign SEG_H_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign SEG_H_s1_master_qreq_vector = 1;

  //SEG_H_s1_reset_n assignment, which is an e_assign
  assign SEG_H_s1_reset_n = reset_n;

  assign SEG_H_s1_chipselect = cpu_data_master_granted_SEG_H_s1;
  //SEG_H_s1_firsttransfer first transaction, which is an e_assign
  assign SEG_H_s1_firsttransfer = SEG_H_s1_begins_xfer ? SEG_H_s1_unreg_firsttransfer : SEG_H_s1_reg_firsttransfer;

  //SEG_H_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign SEG_H_s1_unreg_firsttransfer = ~(SEG_H_s1_slavearbiterlockenable & SEG_H_s1_any_continuerequest);

  //SEG_H_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SEG_H_s1_reg_firsttransfer <= 1'b1;
      else if (SEG_H_s1_begins_xfer)
          SEG_H_s1_reg_firsttransfer <= SEG_H_s1_unreg_firsttransfer;
    end


  //SEG_H_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign SEG_H_s1_beginbursttransfer_internal = SEG_H_s1_begins_xfer;

  //~SEG_H_s1_write_n assignment, which is an e_mux
  assign SEG_H_s1_write_n = ~(((cpu_data_master_granted_SEG_H_s1 & cpu_data_master_write)) & SEG_H_s1_pretend_byte_enable);

  assign shifted_address_to_SEG_H_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //SEG_H_s1_address mux, which is an e_mux
  assign SEG_H_s1_address = shifted_address_to_SEG_H_s1_from_cpu_data_master >> 2;

  //d1_SEG_H_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_SEG_H_s1_end_xfer <= 1;
      else if (1)
          d1_SEG_H_s1_end_xfer <= SEG_H_s1_end_xfer;
    end


  //SEG_H_s1_waits_for_read in a cycle, which is an e_mux
  assign SEG_H_s1_waits_for_read = SEG_H_s1_in_a_read_cycle & SEG_H_s1_begins_xfer;

  //SEG_H_s1_in_a_read_cycle assignment, which is an e_assign
  assign SEG_H_s1_in_a_read_cycle = cpu_data_master_granted_SEG_H_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = SEG_H_s1_in_a_read_cycle;

  //SEG_H_s1_waits_for_write in a cycle, which is an e_mux
  assign SEG_H_s1_waits_for_write = SEG_H_s1_in_a_write_cycle & 0;

  //SEG_H_s1_in_a_write_cycle assignment, which is an e_assign
  assign SEG_H_s1_in_a_write_cycle = cpu_data_master_granted_SEG_H_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = SEG_H_s1_in_a_write_cycle;

  assign wait_for_SEG_H_s1_counter = 0;
  //SEG_H_s1_pretend_byte_enable byte enable port mux, which is an e_mux
  assign SEG_H_s1_pretend_byte_enable = (cpu_data_master_granted_SEG_H_s1)? cpu_data_master_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //SEG_H/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module SEG_l_s1_arbitrator (
                             // inputs:
                              clk,
                              cpu_data_master_address_to_slave,
                              cpu_data_master_byteenable,
                              cpu_data_master_read,
                              cpu_data_master_waitrequest,
                              cpu_data_master_write,
                              cpu_data_master_writedata,
                              reset_n,

                             // outputs:
                              SEG_l_s1_address,
                              SEG_l_s1_chipselect,
                              SEG_l_s1_reset_n,
                              SEG_l_s1_write_n,
                              SEG_l_s1_writedata,
                              cpu_data_master_granted_SEG_l_s1,
                              cpu_data_master_qualified_request_SEG_l_s1,
                              cpu_data_master_read_data_valid_SEG_l_s1,
                              cpu_data_master_requests_SEG_l_s1,
                              d1_SEG_l_s1_end_xfer
                           )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] SEG_l_s1_address;
  output           SEG_l_s1_chipselect;
  output           SEG_l_s1_reset_n;
  output           SEG_l_s1_write_n;
  output  [  7: 0] SEG_l_s1_writedata;
  output           cpu_data_master_granted_SEG_l_s1;
  output           cpu_data_master_qualified_request_SEG_l_s1;
  output           cpu_data_master_read_data_valid_SEG_l_s1;
  output           cpu_data_master_requests_SEG_l_s1;
  output           d1_SEG_l_s1_end_xfer;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] SEG_l_s1_address;
  wire             SEG_l_s1_allgrants;
  wire             SEG_l_s1_allow_new_arb_cycle;
  wire             SEG_l_s1_any_bursting_master_saved_grant;
  wire             SEG_l_s1_any_continuerequest;
  wire             SEG_l_s1_arb_counter_enable;
  reg     [  2: 0] SEG_l_s1_arb_share_counter;
  wire    [  2: 0] SEG_l_s1_arb_share_counter_next_value;
  wire    [  2: 0] SEG_l_s1_arb_share_set_values;
  wire             SEG_l_s1_beginbursttransfer_internal;
  wire             SEG_l_s1_begins_xfer;
  wire             SEG_l_s1_chipselect;
  wire             SEG_l_s1_end_xfer;
  wire             SEG_l_s1_firsttransfer;
  wire             SEG_l_s1_grant_vector;
  wire             SEG_l_s1_in_a_read_cycle;
  wire             SEG_l_s1_in_a_write_cycle;
  wire             SEG_l_s1_master_qreq_vector;
  wire             SEG_l_s1_non_bursting_master_requests;
  wire             SEG_l_s1_pretend_byte_enable;
  reg              SEG_l_s1_reg_firsttransfer;
  wire             SEG_l_s1_reset_n;
  reg              SEG_l_s1_slavearbiterlockenable;
  wire             SEG_l_s1_slavearbiterlockenable2;
  wire             SEG_l_s1_unreg_firsttransfer;
  wire             SEG_l_s1_waits_for_read;
  wire             SEG_l_s1_waits_for_write;
  wire             SEG_l_s1_write_n;
  wire    [  7: 0] SEG_l_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_SEG_l_s1;
  wire             cpu_data_master_qualified_request_SEG_l_s1;
  wire             cpu_data_master_read_data_valid_SEG_l_s1;
  wire             cpu_data_master_requests_SEG_l_s1;
  wire             cpu_data_master_saved_grant_SEG_l_s1;
  reg              d1_SEG_l_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_SEG_l_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 23: 0] shifted_address_to_SEG_l_s1_from_cpu_data_master;
  wire             wait_for_SEG_l_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~SEG_l_s1_end_xfer;
    end


  assign SEG_l_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_SEG_l_s1));
  assign cpu_data_master_requests_SEG_l_s1 = (({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'h81080) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //SEG_l_s1_arb_share_counter set values, which is an e_mux
  assign SEG_l_s1_arb_share_set_values = 1;

  //SEG_l_s1_non_bursting_master_requests mux, which is an e_mux
  assign SEG_l_s1_non_bursting_master_requests = cpu_data_master_requests_SEG_l_s1;

  //SEG_l_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign SEG_l_s1_any_bursting_master_saved_grant = 0;

  //SEG_l_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign SEG_l_s1_arb_share_counter_next_value = SEG_l_s1_firsttransfer ? (SEG_l_s1_arb_share_set_values - 1) : |SEG_l_s1_arb_share_counter ? (SEG_l_s1_arb_share_counter - 1) : 0;

  //SEG_l_s1_allgrants all slave grants, which is an e_mux
  assign SEG_l_s1_allgrants = |SEG_l_s1_grant_vector;

  //SEG_l_s1_end_xfer assignment, which is an e_assign
  assign SEG_l_s1_end_xfer = ~(SEG_l_s1_waits_for_read | SEG_l_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_SEG_l_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_SEG_l_s1 = SEG_l_s1_end_xfer & (~SEG_l_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //SEG_l_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign SEG_l_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_SEG_l_s1 & SEG_l_s1_allgrants) | (end_xfer_arb_share_counter_term_SEG_l_s1 & ~SEG_l_s1_non_bursting_master_requests);

  //SEG_l_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SEG_l_s1_arb_share_counter <= 0;
      else if (SEG_l_s1_arb_counter_enable)
          SEG_l_s1_arb_share_counter <= SEG_l_s1_arb_share_counter_next_value;
    end


  //SEG_l_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SEG_l_s1_slavearbiterlockenable <= 0;
      else if ((|SEG_l_s1_master_qreq_vector & end_xfer_arb_share_counter_term_SEG_l_s1) | (end_xfer_arb_share_counter_term_SEG_l_s1 & ~SEG_l_s1_non_bursting_master_requests))
          SEG_l_s1_slavearbiterlockenable <= |SEG_l_s1_arb_share_counter_next_value;
    end


  //cpu/data_master SEG_l/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = SEG_l_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //SEG_l_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign SEG_l_s1_slavearbiterlockenable2 = |SEG_l_s1_arb_share_counter_next_value;

  //cpu/data_master SEG_l/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = SEG_l_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //SEG_l_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign SEG_l_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_SEG_l_s1 = cpu_data_master_requests_SEG_l_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //SEG_l_s1_writedata mux, which is an e_mux
  assign SEG_l_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_SEG_l_s1 = cpu_data_master_qualified_request_SEG_l_s1;

  //cpu/data_master saved-grant SEG_l/s1, which is an e_assign
  assign cpu_data_master_saved_grant_SEG_l_s1 = cpu_data_master_requests_SEG_l_s1;

  //allow new arb cycle for SEG_l/s1, which is an e_assign
  assign SEG_l_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign SEG_l_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign SEG_l_s1_master_qreq_vector = 1;

  //SEG_l_s1_reset_n assignment, which is an e_assign
  assign SEG_l_s1_reset_n = reset_n;

  assign SEG_l_s1_chipselect = cpu_data_master_granted_SEG_l_s1;
  //SEG_l_s1_firsttransfer first transaction, which is an e_assign
  assign SEG_l_s1_firsttransfer = SEG_l_s1_begins_xfer ? SEG_l_s1_unreg_firsttransfer : SEG_l_s1_reg_firsttransfer;

  //SEG_l_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign SEG_l_s1_unreg_firsttransfer = ~(SEG_l_s1_slavearbiterlockenable & SEG_l_s1_any_continuerequest);

  //SEG_l_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          SEG_l_s1_reg_firsttransfer <= 1'b1;
      else if (SEG_l_s1_begins_xfer)
          SEG_l_s1_reg_firsttransfer <= SEG_l_s1_unreg_firsttransfer;
    end


  //SEG_l_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign SEG_l_s1_beginbursttransfer_internal = SEG_l_s1_begins_xfer;

  //~SEG_l_s1_write_n assignment, which is an e_mux
  assign SEG_l_s1_write_n = ~(((cpu_data_master_granted_SEG_l_s1 & cpu_data_master_write)) & SEG_l_s1_pretend_byte_enable);

  assign shifted_address_to_SEG_l_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //SEG_l_s1_address mux, which is an e_mux
  assign SEG_l_s1_address = shifted_address_to_SEG_l_s1_from_cpu_data_master >> 2;

  //d1_SEG_l_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_SEG_l_s1_end_xfer <= 1;
      else if (1)
          d1_SEG_l_s1_end_xfer <= SEG_l_s1_end_xfer;
    end


  //SEG_l_s1_waits_for_read in a cycle, which is an e_mux
  assign SEG_l_s1_waits_for_read = SEG_l_s1_in_a_read_cycle & SEG_l_s1_begins_xfer;

  //SEG_l_s1_in_a_read_cycle assignment, which is an e_assign
  assign SEG_l_s1_in_a_read_cycle = cpu_data_master_granted_SEG_l_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = SEG_l_s1_in_a_read_cycle;

  //SEG_l_s1_waits_for_write in a cycle, which is an e_mux
  assign SEG_l_s1_waits_for_write = SEG_l_s1_in_a_write_cycle & 0;

  //SEG_l_s1_in_a_write_cycle assignment, which is an e_assign
  assign SEG_l_s1_in_a_write_cycle = cpu_data_master_granted_SEG_l_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = SEG_l_s1_in_a_write_cycle;

  assign wait_for_SEG_l_s1_counter = 0;
  //SEG_l_s1_pretend_byte_enable byte enable port mux, which is an e_mux
  assign SEG_l_s1_pretend_byte_enable = (cpu_data_master_granted_SEG_l_s1)? cpu_data_master_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //SEG_l/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module addr_s1_arbitrator (
                            // inputs:
                             clk,
                             cpu_data_master_address_to_slave,
                             cpu_data_master_read,
                             cpu_data_master_waitrequest,
                             cpu_data_master_write,
                             cpu_data_master_writedata,
                             reset_n,

                            // outputs:
                             addr_s1_address,
                             addr_s1_chipselect,
                             addr_s1_reset_n,
                             addr_s1_write_n,
                             addr_s1_writedata,
                             cpu_data_master_granted_addr_s1,
                             cpu_data_master_qualified_request_addr_s1,
                             cpu_data_master_read_data_valid_addr_s1,
                             cpu_data_master_requests_addr_s1,
                             d1_addr_s1_end_xfer
                          )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] addr_s1_address;
  output           addr_s1_chipselect;
  output           addr_s1_reset_n;
  output           addr_s1_write_n;
  output  [  1: 0] addr_s1_writedata;
  output           cpu_data_master_granted_addr_s1;
  output           cpu_data_master_qualified_request_addr_s1;
  output           cpu_data_master_read_data_valid_addr_s1;
  output           cpu_data_master_requests_addr_s1;
  output           d1_addr_s1_end_xfer;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire    [  1: 0] addr_s1_address;
  wire             addr_s1_allgrants;
  wire             addr_s1_allow_new_arb_cycle;
  wire             addr_s1_any_bursting_master_saved_grant;
  wire             addr_s1_any_continuerequest;
  wire             addr_s1_arb_counter_enable;
  reg     [  2: 0] addr_s1_arb_share_counter;
  wire    [  2: 0] addr_s1_arb_share_counter_next_value;
  wire    [  2: 0] addr_s1_arb_share_set_values;
  wire             addr_s1_beginbursttransfer_internal;
  wire             addr_s1_begins_xfer;
  wire             addr_s1_chipselect;
  wire             addr_s1_end_xfer;
  wire             addr_s1_firsttransfer;
  wire             addr_s1_grant_vector;
  wire             addr_s1_in_a_read_cycle;
  wire             addr_s1_in_a_write_cycle;
  wire             addr_s1_master_qreq_vector;
  wire             addr_s1_non_bursting_master_requests;
  reg              addr_s1_reg_firsttransfer;
  wire             addr_s1_reset_n;
  reg              addr_s1_slavearbiterlockenable;
  wire             addr_s1_slavearbiterlockenable2;
  wire             addr_s1_unreg_firsttransfer;
  wire             addr_s1_waits_for_read;
  wire             addr_s1_waits_for_write;
  wire             addr_s1_write_n;
  wire    [  1: 0] addr_s1_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_addr_s1;
  wire             cpu_data_master_qualified_request_addr_s1;
  wire             cpu_data_master_read_data_valid_addr_s1;
  wire             cpu_data_master_requests_addr_s1;
  wire             cpu_data_master_saved_grant_addr_s1;
  reg              d1_addr_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_addr_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 23: 0] shifted_address_to_addr_s1_from_cpu_data_master;
  wire             wait_for_addr_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~addr_s1_end_xfer;
    end


  assign addr_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_addr_s1));
  assign cpu_data_master_requests_addr_s1 = (({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'h81040) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //addr_s1_arb_share_counter set values, which is an e_mux
  assign addr_s1_arb_share_set_values = 1;

  //addr_s1_non_bursting_master_requests mux, which is an e_mux
  assign addr_s1_non_bursting_master_requests = cpu_data_master_requests_addr_s1;

  //addr_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign addr_s1_any_bursting_master_saved_grant = 0;

  //addr_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign addr_s1_arb_share_counter_next_value = addr_s1_firsttransfer ? (addr_s1_arb_share_set_values - 1) : |addr_s1_arb_share_counter ? (addr_s1_arb_share_counter - 1) : 0;

  //addr_s1_allgrants all slave grants, which is an e_mux
  assign addr_s1_allgrants = |addr_s1_grant_vector;

  //addr_s1_end_xfer assignment, which is an e_assign
  assign addr_s1_end_xfer = ~(addr_s1_waits_for_read | addr_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_addr_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_addr_s1 = addr_s1_end_xfer & (~addr_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //addr_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign addr_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_addr_s1 & addr_s1_allgrants) | (end_xfer_arb_share_counter_term_addr_s1 & ~addr_s1_non_bursting_master_requests);

  //addr_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          addr_s1_arb_share_counter <= 0;
      else if (addr_s1_arb_counter_enable)
          addr_s1_arb_share_counter <= addr_s1_arb_share_counter_next_value;
    end


  //addr_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          addr_s1_slavearbiterlockenable <= 0;
      else if ((|addr_s1_master_qreq_vector & end_xfer_arb_share_counter_term_addr_s1) | (end_xfer_arb_share_counter_term_addr_s1 & ~addr_s1_non_bursting_master_requests))
          addr_s1_slavearbiterlockenable <= |addr_s1_arb_share_counter_next_value;
    end


  //cpu/data_master addr/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = addr_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //addr_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign addr_s1_slavearbiterlockenable2 = |addr_s1_arb_share_counter_next_value;

  //cpu/data_master addr/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = addr_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //addr_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign addr_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_addr_s1 = cpu_data_master_requests_addr_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //addr_s1_writedata mux, which is an e_mux
  assign addr_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_addr_s1 = cpu_data_master_qualified_request_addr_s1;

  //cpu/data_master saved-grant addr/s1, which is an e_assign
  assign cpu_data_master_saved_grant_addr_s1 = cpu_data_master_requests_addr_s1;

  //allow new arb cycle for addr/s1, which is an e_assign
  assign addr_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign addr_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign addr_s1_master_qreq_vector = 1;

  //addr_s1_reset_n assignment, which is an e_assign
  assign addr_s1_reset_n = reset_n;

  assign addr_s1_chipselect = cpu_data_master_granted_addr_s1;
  //addr_s1_firsttransfer first transaction, which is an e_assign
  assign addr_s1_firsttransfer = addr_s1_begins_xfer ? addr_s1_unreg_firsttransfer : addr_s1_reg_firsttransfer;

  //addr_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign addr_s1_unreg_firsttransfer = ~(addr_s1_slavearbiterlockenable & addr_s1_any_continuerequest);

  //addr_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          addr_s1_reg_firsttransfer <= 1'b1;
      else if (addr_s1_begins_xfer)
          addr_s1_reg_firsttransfer <= addr_s1_unreg_firsttransfer;
    end


  //addr_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign addr_s1_beginbursttransfer_internal = addr_s1_begins_xfer;

  //~addr_s1_write_n assignment, which is an e_mux
  assign addr_s1_write_n = ~(cpu_data_master_granted_addr_s1 & cpu_data_master_write);

  assign shifted_address_to_addr_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //addr_s1_address mux, which is an e_mux
  assign addr_s1_address = shifted_address_to_addr_s1_from_cpu_data_master >> 2;

  //d1_addr_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_addr_s1_end_xfer <= 1;
      else if (1)
          d1_addr_s1_end_xfer <= addr_s1_end_xfer;
    end


  //addr_s1_waits_for_read in a cycle, which is an e_mux
  assign addr_s1_waits_for_read = addr_s1_in_a_read_cycle & addr_s1_begins_xfer;

  //addr_s1_in_a_read_cycle assignment, which is an e_assign
  assign addr_s1_in_a_read_cycle = cpu_data_master_granted_addr_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = addr_s1_in_a_read_cycle;

  //addr_s1_waits_for_write in a cycle, which is an e_mux
  assign addr_s1_waits_for_write = addr_s1_in_a_write_cycle & 0;

  //addr_s1_in_a_write_cycle assignment, which is an e_assign
  assign addr_s1_in_a_write_cycle = cpu_data_master_granted_addr_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = addr_s1_in_a_write_cycle;

  assign wait_for_addr_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //addr/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module character_lcd_0_avalon_lcd_slave_arbitrator (
                                                     // inputs:
                                                      character_lcd_0_avalon_lcd_slave_readdata,
                                                      character_lcd_0_avalon_lcd_slave_waitrequest,
                                                      clk,
                                                      cpu_data_master_address_to_slave,
                                                      cpu_data_master_read,
                                                      cpu_data_master_waitrequest,
                                                      cpu_data_master_write,
                                                      cpu_data_master_writedata,
                                                      reset_n,

                                                     // outputs:
                                                      character_lcd_0_avalon_lcd_slave_address,
                                                      character_lcd_0_avalon_lcd_slave_chipselect,
                                                      character_lcd_0_avalon_lcd_slave_read,
                                                      character_lcd_0_avalon_lcd_slave_readdata_from_sa,
                                                      character_lcd_0_avalon_lcd_slave_waitrequest_from_sa,
                                                      character_lcd_0_avalon_lcd_slave_write,
                                                      character_lcd_0_avalon_lcd_slave_writedata,
                                                      cpu_data_master_granted_character_lcd_0_avalon_lcd_slave,
                                                      cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave,
                                                      cpu_data_master_read_data_valid_character_lcd_0_avalon_lcd_slave,
                                                      cpu_data_master_requests_character_lcd_0_avalon_lcd_slave,
                                                      d1_character_lcd_0_avalon_lcd_slave_end_xfer
                                                   )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output           character_lcd_0_avalon_lcd_slave_address;
  output           character_lcd_0_avalon_lcd_slave_chipselect;
  output           character_lcd_0_avalon_lcd_slave_read;
  output  [ 31: 0] character_lcd_0_avalon_lcd_slave_readdata_from_sa;
  output           character_lcd_0_avalon_lcd_slave_waitrequest_from_sa;
  output           character_lcd_0_avalon_lcd_slave_write;
  output  [ 31: 0] character_lcd_0_avalon_lcd_slave_writedata;
  output           cpu_data_master_granted_character_lcd_0_avalon_lcd_slave;
  output           cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave;
  output           cpu_data_master_read_data_valid_character_lcd_0_avalon_lcd_slave;
  output           cpu_data_master_requests_character_lcd_0_avalon_lcd_slave;
  output           d1_character_lcd_0_avalon_lcd_slave_end_xfer;
  input   [ 31: 0] character_lcd_0_avalon_lcd_slave_readdata;
  input            character_lcd_0_avalon_lcd_slave_waitrequest;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire             character_lcd_0_avalon_lcd_slave_address;
  wire             character_lcd_0_avalon_lcd_slave_allgrants;
  wire             character_lcd_0_avalon_lcd_slave_allow_new_arb_cycle;
  wire             character_lcd_0_avalon_lcd_slave_any_bursting_master_saved_grant;
  wire             character_lcd_0_avalon_lcd_slave_any_continuerequest;
  wire             character_lcd_0_avalon_lcd_slave_arb_counter_enable;
  reg     [  2: 0] character_lcd_0_avalon_lcd_slave_arb_share_counter;
  wire    [  2: 0] character_lcd_0_avalon_lcd_slave_arb_share_counter_next_value;
  wire    [  2: 0] character_lcd_0_avalon_lcd_slave_arb_share_set_values;
  wire             character_lcd_0_avalon_lcd_slave_beginbursttransfer_internal;
  wire             character_lcd_0_avalon_lcd_slave_begins_xfer;
  wire             character_lcd_0_avalon_lcd_slave_chipselect;
  wire             character_lcd_0_avalon_lcd_slave_end_xfer;
  wire             character_lcd_0_avalon_lcd_slave_firsttransfer;
  wire             character_lcd_0_avalon_lcd_slave_grant_vector;
  wire             character_lcd_0_avalon_lcd_slave_in_a_read_cycle;
  wire             character_lcd_0_avalon_lcd_slave_in_a_write_cycle;
  wire             character_lcd_0_avalon_lcd_slave_master_qreq_vector;
  wire             character_lcd_0_avalon_lcd_slave_non_bursting_master_requests;
  wire             character_lcd_0_avalon_lcd_slave_read;
  wire    [ 31: 0] character_lcd_0_avalon_lcd_slave_readdata_from_sa;
  reg              character_lcd_0_avalon_lcd_slave_reg_firsttransfer;
  reg              character_lcd_0_avalon_lcd_slave_slavearbiterlockenable;
  wire             character_lcd_0_avalon_lcd_slave_slavearbiterlockenable2;
  wire             character_lcd_0_avalon_lcd_slave_unreg_firsttransfer;
  wire             character_lcd_0_avalon_lcd_slave_waitrequest_from_sa;
  wire             character_lcd_0_avalon_lcd_slave_waits_for_read;
  wire             character_lcd_0_avalon_lcd_slave_waits_for_write;
  wire             character_lcd_0_avalon_lcd_slave_write;
  wire    [ 31: 0] character_lcd_0_avalon_lcd_slave_writedata;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_character_lcd_0_avalon_lcd_slave;
  wire             cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave;
  wire             cpu_data_master_read_data_valid_character_lcd_0_avalon_lcd_slave;
  wire             cpu_data_master_requests_character_lcd_0_avalon_lcd_slave;
  wire             cpu_data_master_saved_grant_character_lcd_0_avalon_lcd_slave;
  reg              d1_character_lcd_0_avalon_lcd_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_character_lcd_0_avalon_lcd_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 23: 0] shifted_address_to_character_lcd_0_avalon_lcd_slave_from_cpu_data_master;
  wire             wait_for_character_lcd_0_avalon_lcd_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~character_lcd_0_avalon_lcd_slave_end_xfer;
    end


  assign character_lcd_0_avalon_lcd_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave));
  //assign character_lcd_0_avalon_lcd_slave_readdata_from_sa = character_lcd_0_avalon_lcd_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign character_lcd_0_avalon_lcd_slave_readdata_from_sa = character_lcd_0_avalon_lcd_slave_readdata;

  assign cpu_data_master_requests_character_lcd_0_avalon_lcd_slave = ({cpu_data_master_address_to_slave[23 : 3] , 3'b0} == 24'h810b8) & (cpu_data_master_read | cpu_data_master_write);
  //assign character_lcd_0_avalon_lcd_slave_waitrequest_from_sa = character_lcd_0_avalon_lcd_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign character_lcd_0_avalon_lcd_slave_waitrequest_from_sa = character_lcd_0_avalon_lcd_slave_waitrequest;

  //character_lcd_0_avalon_lcd_slave_arb_share_counter set values, which is an e_mux
  assign character_lcd_0_avalon_lcd_slave_arb_share_set_values = 1;

  //character_lcd_0_avalon_lcd_slave_non_bursting_master_requests mux, which is an e_mux
  assign character_lcd_0_avalon_lcd_slave_non_bursting_master_requests = cpu_data_master_requests_character_lcd_0_avalon_lcd_slave;

  //character_lcd_0_avalon_lcd_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign character_lcd_0_avalon_lcd_slave_any_bursting_master_saved_grant = 0;

  //character_lcd_0_avalon_lcd_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign character_lcd_0_avalon_lcd_slave_arb_share_counter_next_value = character_lcd_0_avalon_lcd_slave_firsttransfer ? (character_lcd_0_avalon_lcd_slave_arb_share_set_values - 1) : |character_lcd_0_avalon_lcd_slave_arb_share_counter ? (character_lcd_0_avalon_lcd_slave_arb_share_counter - 1) : 0;

  //character_lcd_0_avalon_lcd_slave_allgrants all slave grants, which is an e_mux
  assign character_lcd_0_avalon_lcd_slave_allgrants = |character_lcd_0_avalon_lcd_slave_grant_vector;

  //character_lcd_0_avalon_lcd_slave_end_xfer assignment, which is an e_assign
  assign character_lcd_0_avalon_lcd_slave_end_xfer = ~(character_lcd_0_avalon_lcd_slave_waits_for_read | character_lcd_0_avalon_lcd_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_character_lcd_0_avalon_lcd_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_character_lcd_0_avalon_lcd_slave = character_lcd_0_avalon_lcd_slave_end_xfer & (~character_lcd_0_avalon_lcd_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //character_lcd_0_avalon_lcd_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign character_lcd_0_avalon_lcd_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_character_lcd_0_avalon_lcd_slave & character_lcd_0_avalon_lcd_slave_allgrants) | (end_xfer_arb_share_counter_term_character_lcd_0_avalon_lcd_slave & ~character_lcd_0_avalon_lcd_slave_non_bursting_master_requests);

  //character_lcd_0_avalon_lcd_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          character_lcd_0_avalon_lcd_slave_arb_share_counter <= 0;
      else if (character_lcd_0_avalon_lcd_slave_arb_counter_enable)
          character_lcd_0_avalon_lcd_slave_arb_share_counter <= character_lcd_0_avalon_lcd_slave_arb_share_counter_next_value;
    end


  //character_lcd_0_avalon_lcd_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          character_lcd_0_avalon_lcd_slave_slavearbiterlockenable <= 0;
      else if ((|character_lcd_0_avalon_lcd_slave_master_qreq_vector & end_xfer_arb_share_counter_term_character_lcd_0_avalon_lcd_slave) | (end_xfer_arb_share_counter_term_character_lcd_0_avalon_lcd_slave & ~character_lcd_0_avalon_lcd_slave_non_bursting_master_requests))
          character_lcd_0_avalon_lcd_slave_slavearbiterlockenable <= |character_lcd_0_avalon_lcd_slave_arb_share_counter_next_value;
    end


  //cpu/data_master character_lcd_0/avalon_lcd_slave arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = character_lcd_0_avalon_lcd_slave_slavearbiterlockenable & cpu_data_master_continuerequest;

  //character_lcd_0_avalon_lcd_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign character_lcd_0_avalon_lcd_slave_slavearbiterlockenable2 = |character_lcd_0_avalon_lcd_slave_arb_share_counter_next_value;

  //cpu/data_master character_lcd_0/avalon_lcd_slave arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = character_lcd_0_avalon_lcd_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //character_lcd_0_avalon_lcd_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign character_lcd_0_avalon_lcd_slave_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave = cpu_data_master_requests_character_lcd_0_avalon_lcd_slave & ~((cpu_data_master_read & (~cpu_data_master_waitrequest)) | ((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //character_lcd_0_avalon_lcd_slave_writedata mux, which is an e_mux
  assign character_lcd_0_avalon_lcd_slave_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_character_lcd_0_avalon_lcd_slave = cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave;

  //cpu/data_master saved-grant character_lcd_0/avalon_lcd_slave, which is an e_assign
  assign cpu_data_master_saved_grant_character_lcd_0_avalon_lcd_slave = cpu_data_master_requests_character_lcd_0_avalon_lcd_slave;

  //allow new arb cycle for character_lcd_0/avalon_lcd_slave, which is an e_assign
  assign character_lcd_0_avalon_lcd_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign character_lcd_0_avalon_lcd_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign character_lcd_0_avalon_lcd_slave_master_qreq_vector = 1;

  assign character_lcd_0_avalon_lcd_slave_chipselect = cpu_data_master_granted_character_lcd_0_avalon_lcd_slave;
  //character_lcd_0_avalon_lcd_slave_firsttransfer first transaction, which is an e_assign
  assign character_lcd_0_avalon_lcd_slave_firsttransfer = character_lcd_0_avalon_lcd_slave_begins_xfer ? character_lcd_0_avalon_lcd_slave_unreg_firsttransfer : character_lcd_0_avalon_lcd_slave_reg_firsttransfer;

  //character_lcd_0_avalon_lcd_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign character_lcd_0_avalon_lcd_slave_unreg_firsttransfer = ~(character_lcd_0_avalon_lcd_slave_slavearbiterlockenable & character_lcd_0_avalon_lcd_slave_any_continuerequest);

  //character_lcd_0_avalon_lcd_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          character_lcd_0_avalon_lcd_slave_reg_firsttransfer <= 1'b1;
      else if (character_lcd_0_avalon_lcd_slave_begins_xfer)
          character_lcd_0_avalon_lcd_slave_reg_firsttransfer <= character_lcd_0_avalon_lcd_slave_unreg_firsttransfer;
    end


  //character_lcd_0_avalon_lcd_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign character_lcd_0_avalon_lcd_slave_beginbursttransfer_internal = character_lcd_0_avalon_lcd_slave_begins_xfer;

  //character_lcd_0_avalon_lcd_slave_read assignment, which is an e_mux
  assign character_lcd_0_avalon_lcd_slave_read = cpu_data_master_granted_character_lcd_0_avalon_lcd_slave & cpu_data_master_read;

  //character_lcd_0_avalon_lcd_slave_write assignment, which is an e_mux
  assign character_lcd_0_avalon_lcd_slave_write = cpu_data_master_granted_character_lcd_0_avalon_lcd_slave & cpu_data_master_write;

  assign shifted_address_to_character_lcd_0_avalon_lcd_slave_from_cpu_data_master = cpu_data_master_address_to_slave;
  //character_lcd_0_avalon_lcd_slave_address mux, which is an e_mux
  assign character_lcd_0_avalon_lcd_slave_address = shifted_address_to_character_lcd_0_avalon_lcd_slave_from_cpu_data_master >> 2;

  //d1_character_lcd_0_avalon_lcd_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_character_lcd_0_avalon_lcd_slave_end_xfer <= 1;
      else if (1)
          d1_character_lcd_0_avalon_lcd_slave_end_xfer <= character_lcd_0_avalon_lcd_slave_end_xfer;
    end


  //character_lcd_0_avalon_lcd_slave_waits_for_read in a cycle, which is an e_mux
  assign character_lcd_0_avalon_lcd_slave_waits_for_read = character_lcd_0_avalon_lcd_slave_in_a_read_cycle & character_lcd_0_avalon_lcd_slave_waitrequest_from_sa;

  //character_lcd_0_avalon_lcd_slave_in_a_read_cycle assignment, which is an e_assign
  assign character_lcd_0_avalon_lcd_slave_in_a_read_cycle = cpu_data_master_granted_character_lcd_0_avalon_lcd_slave & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = character_lcd_0_avalon_lcd_slave_in_a_read_cycle;

  //character_lcd_0_avalon_lcd_slave_waits_for_write in a cycle, which is an e_mux
  assign character_lcd_0_avalon_lcd_slave_waits_for_write = character_lcd_0_avalon_lcd_slave_in_a_write_cycle & character_lcd_0_avalon_lcd_slave_waitrequest_from_sa;

  //character_lcd_0_avalon_lcd_slave_in_a_write_cycle assignment, which is an e_assign
  assign character_lcd_0_avalon_lcd_slave_in_a_write_cycle = cpu_data_master_granted_character_lcd_0_avalon_lcd_slave & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = character_lcd_0_avalon_lcd_slave_in_a_write_cycle;

  assign wait_for_character_lcd_0_avalon_lcd_slave_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //character_lcd_0/avalon_lcd_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module testPro_reset_clk_domain_synch_module (
                                               // inputs:
                                                clk,
                                                data_in,
                                                reset_n,

                                               // outputs:
                                                data_out
                                             )
;

  output           data_out;
  input            clk;
  input            data_in;
  input            reset_n;

  reg              data_in_d1 /* synthesis ALTERA_ATTRIBUTE = "MAX_DELAY=\"100ns\" ; PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  reg              data_out /* synthesis ALTERA_ATTRIBUTE = "PRESERVE_REGISTER=ON ; SUPPRESS_DA_RULE_INTERNAL=R101"  */;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_in_d1 <= 0;
      else if (1)
          data_in_d1 <= data_in;
    end


  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          data_out <= 0;
      else if (1)
          data_out <= data_in_d1;
    end



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_jtag_debug_module_arbitrator (
                                          // inputs:
                                           clk,
                                           cpu_data_master_address_to_slave,
                                           cpu_data_master_byteenable,
                                           cpu_data_master_debugaccess,
                                           cpu_data_master_read,
                                           cpu_data_master_waitrequest,
                                           cpu_data_master_write,
                                           cpu_data_master_writedata,
                                           cpu_instruction_master_address_to_slave,
                                           cpu_instruction_master_latency_counter,
                                           cpu_instruction_master_read,
                                           cpu_jtag_debug_module_readdata,
                                           cpu_jtag_debug_module_resetrequest,
                                           reset_n,

                                          // outputs:
                                           cpu_data_master_granted_cpu_jtag_debug_module,
                                           cpu_data_master_qualified_request_cpu_jtag_debug_module,
                                           cpu_data_master_read_data_valid_cpu_jtag_debug_module,
                                           cpu_data_master_requests_cpu_jtag_debug_module,
                                           cpu_instruction_master_granted_cpu_jtag_debug_module,
                                           cpu_instruction_master_qualified_request_cpu_jtag_debug_module,
                                           cpu_instruction_master_read_data_valid_cpu_jtag_debug_module,
                                           cpu_instruction_master_requests_cpu_jtag_debug_module,
                                           cpu_jtag_debug_module_address,
                                           cpu_jtag_debug_module_begintransfer,
                                           cpu_jtag_debug_module_byteenable,
                                           cpu_jtag_debug_module_chipselect,
                                           cpu_jtag_debug_module_debugaccess,
                                           cpu_jtag_debug_module_readdata_from_sa,
                                           cpu_jtag_debug_module_reset,
                                           cpu_jtag_debug_module_reset_n,
                                           cpu_jtag_debug_module_resetrequest_from_sa,
                                           cpu_jtag_debug_module_write,
                                           cpu_jtag_debug_module_writedata,
                                           d1_cpu_jtag_debug_module_end_xfer
                                        )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output           cpu_data_master_granted_cpu_jtag_debug_module;
  output           cpu_data_master_qualified_request_cpu_jtag_debug_module;
  output           cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  output           cpu_data_master_requests_cpu_jtag_debug_module;
  output           cpu_instruction_master_granted_cpu_jtag_debug_module;
  output           cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  output           cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  output           cpu_instruction_master_requests_cpu_jtag_debug_module;
  output  [  8: 0] cpu_jtag_debug_module_address;
  output           cpu_jtag_debug_module_begintransfer;
  output  [  3: 0] cpu_jtag_debug_module_byteenable;
  output           cpu_jtag_debug_module_chipselect;
  output           cpu_jtag_debug_module_debugaccess;
  output  [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  output           cpu_jtag_debug_module_reset;
  output           cpu_jtag_debug_module_reset_n;
  output           cpu_jtag_debug_module_resetrequest_from_sa;
  output           cpu_jtag_debug_module_write;
  output  [ 31: 0] cpu_jtag_debug_module_writedata;
  output           d1_cpu_jtag_debug_module_end_xfer;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input            cpu_data_master_debugaccess;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 23: 0] cpu_instruction_master_address_to_slave;
  input   [  1: 0] cpu_instruction_master_latency_counter;
  input            cpu_instruction_master_read;
  input   [ 31: 0] cpu_jtag_debug_module_readdata;
  input            cpu_jtag_debug_module_resetrequest;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_cpu_jtag_debug_module;
  wire             cpu_data_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_data_master_requests_cpu_jtag_debug_module;
  wire             cpu_data_master_saved_grant_cpu_jtag_debug_module;
  wire             cpu_instruction_master_arbiterlock;
  wire             cpu_instruction_master_arbiterlock2;
  wire             cpu_instruction_master_continuerequest;
  wire             cpu_instruction_master_granted_cpu_jtag_debug_module;
  wire             cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_instruction_master_requests_cpu_jtag_debug_module;
  wire             cpu_instruction_master_saved_grant_cpu_jtag_debug_module;
  wire    [  8: 0] cpu_jtag_debug_module_address;
  wire             cpu_jtag_debug_module_allgrants;
  wire             cpu_jtag_debug_module_allow_new_arb_cycle;
  wire             cpu_jtag_debug_module_any_bursting_master_saved_grant;
  wire             cpu_jtag_debug_module_any_continuerequest;
  reg     [  1: 0] cpu_jtag_debug_module_arb_addend;
  wire             cpu_jtag_debug_module_arb_counter_enable;
  reg     [  2: 0] cpu_jtag_debug_module_arb_share_counter;
  wire    [  2: 0] cpu_jtag_debug_module_arb_share_counter_next_value;
  wire    [  2: 0] cpu_jtag_debug_module_arb_share_set_values;
  wire    [  1: 0] cpu_jtag_debug_module_arb_winner;
  wire             cpu_jtag_debug_module_arbitration_holdoff_internal;
  wire             cpu_jtag_debug_module_beginbursttransfer_internal;
  wire             cpu_jtag_debug_module_begins_xfer;
  wire             cpu_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_jtag_debug_module_byteenable;
  wire             cpu_jtag_debug_module_chipselect;
  wire    [  3: 0] cpu_jtag_debug_module_chosen_master_double_vector;
  wire    [  1: 0] cpu_jtag_debug_module_chosen_master_rot_left;
  wire             cpu_jtag_debug_module_debugaccess;
  wire             cpu_jtag_debug_module_end_xfer;
  wire             cpu_jtag_debug_module_firsttransfer;
  wire    [  1: 0] cpu_jtag_debug_module_grant_vector;
  wire             cpu_jtag_debug_module_in_a_read_cycle;
  wire             cpu_jtag_debug_module_in_a_write_cycle;
  wire    [  1: 0] cpu_jtag_debug_module_master_qreq_vector;
  wire             cpu_jtag_debug_module_non_bursting_master_requests;
  wire    [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  reg              cpu_jtag_debug_module_reg_firsttransfer;
  wire             cpu_jtag_debug_module_reset;
  wire             cpu_jtag_debug_module_reset_n;
  wire             cpu_jtag_debug_module_resetrequest_from_sa;
  reg     [  1: 0] cpu_jtag_debug_module_saved_chosen_master_vector;
  reg              cpu_jtag_debug_module_slavearbiterlockenable;
  wire             cpu_jtag_debug_module_slavearbiterlockenable2;
  wire             cpu_jtag_debug_module_unreg_firsttransfer;
  wire             cpu_jtag_debug_module_waits_for_read;
  wire             cpu_jtag_debug_module_waits_for_write;
  wire             cpu_jtag_debug_module_write;
  wire    [ 31: 0] cpu_jtag_debug_module_writedata;
  reg              d1_cpu_jtag_debug_module_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_cpu_jtag_debug_module;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module;
  reg              last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module;
  wire    [ 23: 0] shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master;
  wire    [ 23: 0] shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master;
  wire             wait_for_cpu_jtag_debug_module_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~cpu_jtag_debug_module_end_xfer;
    end


  assign cpu_jtag_debug_module_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_cpu_jtag_debug_module | cpu_instruction_master_qualified_request_cpu_jtag_debug_module));
  //assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_jtag_debug_module_readdata_from_sa = cpu_jtag_debug_module_readdata;

  assign cpu_data_master_requests_cpu_jtag_debug_module = ({cpu_data_master_address_to_slave[23 : 11] , 11'b0} == 24'h80800) & (cpu_data_master_read | cpu_data_master_write);
  //cpu_jtag_debug_module_arb_share_counter set values, which is an e_mux
  assign cpu_jtag_debug_module_arb_share_set_values = 1;

  //cpu_jtag_debug_module_non_bursting_master_requests mux, which is an e_mux
  assign cpu_jtag_debug_module_non_bursting_master_requests = cpu_data_master_requests_cpu_jtag_debug_module |
    cpu_instruction_master_requests_cpu_jtag_debug_module |
    cpu_data_master_requests_cpu_jtag_debug_module |
    cpu_instruction_master_requests_cpu_jtag_debug_module;

  //cpu_jtag_debug_module_any_bursting_master_saved_grant mux, which is an e_mux
  assign cpu_jtag_debug_module_any_bursting_master_saved_grant = 0;

  //cpu_jtag_debug_module_arb_share_counter_next_value assignment, which is an e_assign
  assign cpu_jtag_debug_module_arb_share_counter_next_value = cpu_jtag_debug_module_firsttransfer ? (cpu_jtag_debug_module_arb_share_set_values - 1) : |cpu_jtag_debug_module_arb_share_counter ? (cpu_jtag_debug_module_arb_share_counter - 1) : 0;

  //cpu_jtag_debug_module_allgrants all slave grants, which is an e_mux
  assign cpu_jtag_debug_module_allgrants = |cpu_jtag_debug_module_grant_vector |
    |cpu_jtag_debug_module_grant_vector |
    |cpu_jtag_debug_module_grant_vector |
    |cpu_jtag_debug_module_grant_vector;

  //cpu_jtag_debug_module_end_xfer assignment, which is an e_assign
  assign cpu_jtag_debug_module_end_xfer = ~(cpu_jtag_debug_module_waits_for_read | cpu_jtag_debug_module_waits_for_write);

  //end_xfer_arb_share_counter_term_cpu_jtag_debug_module arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_cpu_jtag_debug_module = cpu_jtag_debug_module_end_xfer & (~cpu_jtag_debug_module_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //cpu_jtag_debug_module_arb_share_counter arbitration counter enable, which is an e_assign
  assign cpu_jtag_debug_module_arb_counter_enable = (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & cpu_jtag_debug_module_allgrants) | (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & ~cpu_jtag_debug_module_non_bursting_master_requests);

  //cpu_jtag_debug_module_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_arb_share_counter <= 0;
      else if (cpu_jtag_debug_module_arb_counter_enable)
          cpu_jtag_debug_module_arb_share_counter <= cpu_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu_jtag_debug_module_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_slavearbiterlockenable <= 0;
      else if ((|cpu_jtag_debug_module_master_qreq_vector & end_xfer_arb_share_counter_term_cpu_jtag_debug_module) | (end_xfer_arb_share_counter_term_cpu_jtag_debug_module & ~cpu_jtag_debug_module_non_bursting_master_requests))
          cpu_jtag_debug_module_slavearbiterlockenable <= |cpu_jtag_debug_module_arb_share_counter_next_value;
    end


  //cpu/data_master cpu/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_data_master_continuerequest;

  //cpu_jtag_debug_module_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign cpu_jtag_debug_module_slavearbiterlockenable2 = |cpu_jtag_debug_module_arb_share_counter_next_value;

  //cpu/data_master cpu/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = cpu_jtag_debug_module_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //cpu/instruction_master cpu/jtag_debug_module arbiterlock, which is an e_assign
  assign cpu_instruction_master_arbiterlock = cpu_jtag_debug_module_slavearbiterlockenable & cpu_instruction_master_continuerequest;

  //cpu/instruction_master cpu/jtag_debug_module arbiterlock2, which is an e_assign
  assign cpu_instruction_master_arbiterlock2 = cpu_jtag_debug_module_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;

  //cpu/instruction_master granted cpu/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= 0;
      else if (1)
          last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module <= cpu_instruction_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_instruction_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module;
    end


  //cpu_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_cpu_jtag_debug_module & cpu_instruction_master_requests_cpu_jtag_debug_module;

  //cpu_jtag_debug_module_any_continuerequest at least one master continues requesting, which is an e_mux
  assign cpu_jtag_debug_module_any_continuerequest = cpu_instruction_master_continuerequest |
    cpu_data_master_continuerequest;

  assign cpu_data_master_qualified_request_cpu_jtag_debug_module = cpu_data_master_requests_cpu_jtag_debug_module & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write) | cpu_instruction_master_arbiterlock);
  //cpu_jtag_debug_module_writedata mux, which is an e_mux
  assign cpu_jtag_debug_module_writedata = cpu_data_master_writedata;

  //mux cpu_jtag_debug_module_debugaccess, which is an e_mux
  assign cpu_jtag_debug_module_debugaccess = cpu_data_master_debugaccess;

  assign cpu_instruction_master_requests_cpu_jtag_debug_module = (({cpu_instruction_master_address_to_slave[23 : 11] , 11'b0} == 24'h80800) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
  //cpu/data_master granted cpu/jtag_debug_module last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= 0;
      else if (1)
          last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module <= cpu_data_master_saved_grant_cpu_jtag_debug_module ? 1 : (cpu_jtag_debug_module_arbitration_holdoff_internal | ~cpu_data_master_requests_cpu_jtag_debug_module) ? 0 : last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module;
    end


  //cpu_data_master_continuerequest continued request, which is an e_mux
  assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_cpu_jtag_debug_module & cpu_data_master_requests_cpu_jtag_debug_module;

  assign cpu_instruction_master_qualified_request_cpu_jtag_debug_module = cpu_instruction_master_requests_cpu_jtag_debug_module & ~((cpu_instruction_master_read & ((cpu_instruction_master_latency_counter != 0))) | cpu_data_master_arbiterlock);
  //local readdatavalid cpu_instruction_master_read_data_valid_cpu_jtag_debug_module, which is an e_mux
  assign cpu_instruction_master_read_data_valid_cpu_jtag_debug_module = cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read & ~cpu_jtag_debug_module_waits_for_read;

  //allow new arb cycle for cpu/jtag_debug_module, which is an e_assign
  assign cpu_jtag_debug_module_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;

  //cpu/instruction_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign
  assign cpu_jtag_debug_module_master_qreq_vector[0] = cpu_instruction_master_qualified_request_cpu_jtag_debug_module;

  //cpu/instruction_master grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_instruction_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[0];

  //cpu/instruction_master saved-grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_instruction_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[0] && cpu_instruction_master_requests_cpu_jtag_debug_module;

  //cpu/data_master assignment into master qualified-requests vector for cpu/jtag_debug_module, which is an e_assign
  assign cpu_jtag_debug_module_master_qreq_vector[1] = cpu_data_master_qualified_request_cpu_jtag_debug_module;

  //cpu/data_master grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_data_master_granted_cpu_jtag_debug_module = cpu_jtag_debug_module_grant_vector[1];

  //cpu/data_master saved-grant cpu/jtag_debug_module, which is an e_assign
  assign cpu_data_master_saved_grant_cpu_jtag_debug_module = cpu_jtag_debug_module_arb_winner[1] && cpu_data_master_requests_cpu_jtag_debug_module;

  //cpu/jtag_debug_module chosen-master double-vector, which is an e_assign
  assign cpu_jtag_debug_module_chosen_master_double_vector = {cpu_jtag_debug_module_master_qreq_vector, cpu_jtag_debug_module_master_qreq_vector} & ({~cpu_jtag_debug_module_master_qreq_vector, ~cpu_jtag_debug_module_master_qreq_vector} + cpu_jtag_debug_module_arb_addend);

  //stable onehot encoding of arb winner
  assign cpu_jtag_debug_module_arb_winner = (cpu_jtag_debug_module_allow_new_arb_cycle & | cpu_jtag_debug_module_grant_vector) ? cpu_jtag_debug_module_grant_vector : cpu_jtag_debug_module_saved_chosen_master_vector;

  //saved cpu_jtag_debug_module_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_saved_chosen_master_vector <= 0;
      else if (cpu_jtag_debug_module_allow_new_arb_cycle)
          cpu_jtag_debug_module_saved_chosen_master_vector <= |cpu_jtag_debug_module_grant_vector ? cpu_jtag_debug_module_grant_vector : cpu_jtag_debug_module_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign cpu_jtag_debug_module_grant_vector = {(cpu_jtag_debug_module_chosen_master_double_vector[1] | cpu_jtag_debug_module_chosen_master_double_vector[3]),
    (cpu_jtag_debug_module_chosen_master_double_vector[0] | cpu_jtag_debug_module_chosen_master_double_vector[2])};

  //cpu/jtag_debug_module chosen master rotated left, which is an e_assign
  assign cpu_jtag_debug_module_chosen_master_rot_left = (cpu_jtag_debug_module_arb_winner << 1) ? (cpu_jtag_debug_module_arb_winner << 1) : 1;

  //cpu/jtag_debug_module's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_arb_addend <= 1;
      else if (|cpu_jtag_debug_module_grant_vector)
          cpu_jtag_debug_module_arb_addend <= cpu_jtag_debug_module_end_xfer? cpu_jtag_debug_module_chosen_master_rot_left : cpu_jtag_debug_module_grant_vector;
    end


  assign cpu_jtag_debug_module_begintransfer = cpu_jtag_debug_module_begins_xfer;
  //assign lhs ~cpu_jtag_debug_module_reset of type reset_n to cpu_jtag_debug_module_reset_n, which is an e_assign
  assign cpu_jtag_debug_module_reset = ~cpu_jtag_debug_module_reset_n;

  //cpu_jtag_debug_module_reset_n assignment, which is an e_assign
  assign cpu_jtag_debug_module_reset_n = reset_n;

  //assign cpu_jtag_debug_module_resetrequest_from_sa = cpu_jtag_debug_module_resetrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign cpu_jtag_debug_module_resetrequest_from_sa = cpu_jtag_debug_module_resetrequest;

  assign cpu_jtag_debug_module_chipselect = cpu_data_master_granted_cpu_jtag_debug_module | cpu_instruction_master_granted_cpu_jtag_debug_module;
  //cpu_jtag_debug_module_firsttransfer first transaction, which is an e_assign
  assign cpu_jtag_debug_module_firsttransfer = cpu_jtag_debug_module_begins_xfer ? cpu_jtag_debug_module_unreg_firsttransfer : cpu_jtag_debug_module_reg_firsttransfer;

  //cpu_jtag_debug_module_unreg_firsttransfer first transaction, which is an e_assign
  assign cpu_jtag_debug_module_unreg_firsttransfer = ~(cpu_jtag_debug_module_slavearbiterlockenable & cpu_jtag_debug_module_any_continuerequest);

  //cpu_jtag_debug_module_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_jtag_debug_module_reg_firsttransfer <= 1'b1;
      else if (cpu_jtag_debug_module_begins_xfer)
          cpu_jtag_debug_module_reg_firsttransfer <= cpu_jtag_debug_module_unreg_firsttransfer;
    end


  //cpu_jtag_debug_module_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign cpu_jtag_debug_module_beginbursttransfer_internal = cpu_jtag_debug_module_begins_xfer;

  //cpu_jtag_debug_module_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign cpu_jtag_debug_module_arbitration_holdoff_internal = cpu_jtag_debug_module_begins_xfer & cpu_jtag_debug_module_firsttransfer;

  //cpu_jtag_debug_module_write assignment, which is an e_mux
  assign cpu_jtag_debug_module_write = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write;

  assign shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master = cpu_data_master_address_to_slave;
  //cpu_jtag_debug_module_address mux, which is an e_mux
  assign cpu_jtag_debug_module_address = (cpu_data_master_granted_cpu_jtag_debug_module)? (shifted_address_to_cpu_jtag_debug_module_from_cpu_data_master >> 2) :
    (shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master >> 2);

  assign shifted_address_to_cpu_jtag_debug_module_from_cpu_instruction_master = cpu_instruction_master_address_to_slave;
  //d1_cpu_jtag_debug_module_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_cpu_jtag_debug_module_end_xfer <= 1;
      else if (1)
          d1_cpu_jtag_debug_module_end_xfer <= cpu_jtag_debug_module_end_xfer;
    end


  //cpu_jtag_debug_module_waits_for_read in a cycle, which is an e_mux
  assign cpu_jtag_debug_module_waits_for_read = cpu_jtag_debug_module_in_a_read_cycle & cpu_jtag_debug_module_begins_xfer;

  //cpu_jtag_debug_module_in_a_read_cycle assignment, which is an e_assign
  assign cpu_jtag_debug_module_in_a_read_cycle = (cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_read) | (cpu_instruction_master_granted_cpu_jtag_debug_module & cpu_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = cpu_jtag_debug_module_in_a_read_cycle;

  //cpu_jtag_debug_module_waits_for_write in a cycle, which is an e_mux
  assign cpu_jtag_debug_module_waits_for_write = cpu_jtag_debug_module_in_a_write_cycle & 0;

  //cpu_jtag_debug_module_in_a_write_cycle assignment, which is an e_assign
  assign cpu_jtag_debug_module_in_a_write_cycle = cpu_data_master_granted_cpu_jtag_debug_module & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = cpu_jtag_debug_module_in_a_write_cycle;

  assign wait_for_cpu_jtag_debug_module_counter = 0;
  //cpu_jtag_debug_module_byteenable byte enable port mux, which is an e_mux
  assign cpu_jtag_debug_module_byteenable = (cpu_data_master_granted_cpu_jtag_debug_module)? cpu_data_master_byteenable :
    -1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu/jtag_debug_module enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_granted_cpu_jtag_debug_module + cpu_instruction_master_granted_cpu_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_saved_grant_cpu_jtag_debug_module + cpu_instruction_master_saved_grant_cpu_jtag_debug_module > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_data_master_arbitrator (
                                    // inputs:
                                     Din_s1_readdata_from_sa,
                                     character_lcd_0_avalon_lcd_slave_readdata_from_sa,
                                     character_lcd_0_avalon_lcd_slave_waitrequest_from_sa,
                                     clk,
                                     cpu_data_master_address,
                                     cpu_data_master_byteenable_flash_s1,
                                     cpu_data_master_byteenable_sram_0_avalon_sram_slave,
                                     cpu_data_master_debugaccess,
                                     cpu_data_master_granted_Din_s1,
                                     cpu_data_master_granted_Dout_s1,
                                     cpu_data_master_granted_SEG_H_s1,
                                     cpu_data_master_granted_SEG_l_s1,
                                     cpu_data_master_granted_addr_s1,
                                     cpu_data_master_granted_character_lcd_0_avalon_lcd_slave,
                                     cpu_data_master_granted_cpu_jtag_debug_module,
                                     cpu_data_master_granted_flash_s1,
                                     cpu_data_master_granted_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_granted_nCS_s1,
                                     cpu_data_master_granted_nRD_s1,
                                     cpu_data_master_granted_nWR_s1,
                                     cpu_data_master_granted_ps2_0_avalon_PS2_slave,
                                     cpu_data_master_granted_sram_0_avalon_sram_slave,
                                     cpu_data_master_granted_sysid_control_slave,
                                     cpu_data_master_granted_timer_s1,
                                     cpu_data_master_qualified_request_Din_s1,
                                     cpu_data_master_qualified_request_Dout_s1,
                                     cpu_data_master_qualified_request_SEG_H_s1,
                                     cpu_data_master_qualified_request_SEG_l_s1,
                                     cpu_data_master_qualified_request_addr_s1,
                                     cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave,
                                     cpu_data_master_qualified_request_cpu_jtag_debug_module,
                                     cpu_data_master_qualified_request_flash_s1,
                                     cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_qualified_request_nCS_s1,
                                     cpu_data_master_qualified_request_nRD_s1,
                                     cpu_data_master_qualified_request_nWR_s1,
                                     cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave,
                                     cpu_data_master_qualified_request_sram_0_avalon_sram_slave,
                                     cpu_data_master_qualified_request_sysid_control_slave,
                                     cpu_data_master_qualified_request_timer_s1,
                                     cpu_data_master_read,
                                     cpu_data_master_read_data_valid_Din_s1,
                                     cpu_data_master_read_data_valid_Dout_s1,
                                     cpu_data_master_read_data_valid_SEG_H_s1,
                                     cpu_data_master_read_data_valid_SEG_l_s1,
                                     cpu_data_master_read_data_valid_addr_s1,
                                     cpu_data_master_read_data_valid_character_lcd_0_avalon_lcd_slave,
                                     cpu_data_master_read_data_valid_cpu_jtag_debug_module,
                                     cpu_data_master_read_data_valid_flash_s1,
                                     cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_read_data_valid_nCS_s1,
                                     cpu_data_master_read_data_valid_nRD_s1,
                                     cpu_data_master_read_data_valid_nWR_s1,
                                     cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave,
                                     cpu_data_master_read_data_valid_sram_0_avalon_sram_slave,
                                     cpu_data_master_read_data_valid_sysid_control_slave,
                                     cpu_data_master_read_data_valid_timer_s1,
                                     cpu_data_master_requests_Din_s1,
                                     cpu_data_master_requests_Dout_s1,
                                     cpu_data_master_requests_SEG_H_s1,
                                     cpu_data_master_requests_SEG_l_s1,
                                     cpu_data_master_requests_addr_s1,
                                     cpu_data_master_requests_character_lcd_0_avalon_lcd_slave,
                                     cpu_data_master_requests_cpu_jtag_debug_module,
                                     cpu_data_master_requests_flash_s1,
                                     cpu_data_master_requests_jtag_uart_avalon_jtag_slave,
                                     cpu_data_master_requests_nCS_s1,
                                     cpu_data_master_requests_nRD_s1,
                                     cpu_data_master_requests_nWR_s1,
                                     cpu_data_master_requests_ps2_0_avalon_PS2_slave,
                                     cpu_data_master_requests_sram_0_avalon_sram_slave,
                                     cpu_data_master_requests_sysid_control_slave,
                                     cpu_data_master_requests_timer_s1,
                                     cpu_data_master_write,
                                     cpu_data_master_writedata,
                                     cpu_jtag_debug_module_readdata_from_sa,
                                     d1_Din_s1_end_xfer,
                                     d1_Dout_s1_end_xfer,
                                     d1_SEG_H_s1_end_xfer,
                                     d1_SEG_l_s1_end_xfer,
                                     d1_addr_s1_end_xfer,
                                     d1_character_lcd_0_avalon_lcd_slave_end_xfer,
                                     d1_cpu_jtag_debug_module_end_xfer,
                                     d1_jtag_uart_avalon_jtag_slave_end_xfer,
                                     d1_nCS_s1_end_xfer,
                                     d1_nRD_s1_end_xfer,
                                     d1_nWR_s1_end_xfer,
                                     d1_ps2_0_avalon_PS2_slave_end_xfer,
                                     d1_sram_0_avalon_sram_slave_end_xfer,
                                     d1_sysid_control_slave_end_xfer,
                                     d1_timer_s1_end_xfer,
                                     d1_tristate_bridge_avalon_slave_end_xfer,
                                     incoming_data_to_and_from_the_flash_with_Xs_converted_to_0,
                                     jtag_uart_avalon_jtag_slave_irq_from_sa,
                                     jtag_uart_avalon_jtag_slave_readdata_from_sa,
                                     jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
                                     ps2_0_avalon_PS2_slave_irq_from_sa,
                                     ps2_0_avalon_PS2_slave_readdata_from_sa,
                                     ps2_0_avalon_PS2_slave_waitrequest_from_sa,
                                     registered_cpu_data_master_read_data_valid_flash_s1,
                                     registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave,
                                     registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave,
                                     reset_n,
                                     sram_0_avalon_sram_slave_readdata_from_sa,
                                     sysid_control_slave_readdata_from_sa,
                                     timer_s1_irq_from_sa,
                                     timer_s1_readdata_from_sa,

                                    // outputs:
                                     cpu_data_master_address_to_slave,
                                     cpu_data_master_dbs_address,
                                     cpu_data_master_dbs_write_16,
                                     cpu_data_master_dbs_write_8,
                                     cpu_data_master_irq,
                                     cpu_data_master_no_byte_enables_and_last_term,
                                     cpu_data_master_readdata,
                                     cpu_data_master_waitrequest
                                  )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [ 23: 0] cpu_data_master_address_to_slave;
  output  [  1: 0] cpu_data_master_dbs_address;
  output  [ 15: 0] cpu_data_master_dbs_write_16;
  output  [  7: 0] cpu_data_master_dbs_write_8;
  output  [ 31: 0] cpu_data_master_irq;
  output           cpu_data_master_no_byte_enables_and_last_term;
  output  [ 31: 0] cpu_data_master_readdata;
  output           cpu_data_master_waitrequest;
  input   [  7: 0] Din_s1_readdata_from_sa;
  input   [ 31: 0] character_lcd_0_avalon_lcd_slave_readdata_from_sa;
  input            character_lcd_0_avalon_lcd_slave_waitrequest_from_sa;
  input            clk;
  input   [ 23: 0] cpu_data_master_address;
  input            cpu_data_master_byteenable_flash_s1;
  input   [  1: 0] cpu_data_master_byteenable_sram_0_avalon_sram_slave;
  input            cpu_data_master_debugaccess;
  input            cpu_data_master_granted_Din_s1;
  input            cpu_data_master_granted_Dout_s1;
  input            cpu_data_master_granted_SEG_H_s1;
  input            cpu_data_master_granted_SEG_l_s1;
  input            cpu_data_master_granted_addr_s1;
  input            cpu_data_master_granted_character_lcd_0_avalon_lcd_slave;
  input            cpu_data_master_granted_cpu_jtag_debug_module;
  input            cpu_data_master_granted_flash_s1;
  input            cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_granted_nCS_s1;
  input            cpu_data_master_granted_nRD_s1;
  input            cpu_data_master_granted_nWR_s1;
  input            cpu_data_master_granted_ps2_0_avalon_PS2_slave;
  input            cpu_data_master_granted_sram_0_avalon_sram_slave;
  input            cpu_data_master_granted_sysid_control_slave;
  input            cpu_data_master_granted_timer_s1;
  input            cpu_data_master_qualified_request_Din_s1;
  input            cpu_data_master_qualified_request_Dout_s1;
  input            cpu_data_master_qualified_request_SEG_H_s1;
  input            cpu_data_master_qualified_request_SEG_l_s1;
  input            cpu_data_master_qualified_request_addr_s1;
  input            cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave;
  input            cpu_data_master_qualified_request_cpu_jtag_debug_module;
  input            cpu_data_master_qualified_request_flash_s1;
  input            cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_qualified_request_nCS_s1;
  input            cpu_data_master_qualified_request_nRD_s1;
  input            cpu_data_master_qualified_request_nWR_s1;
  input            cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave;
  input            cpu_data_master_qualified_request_sram_0_avalon_sram_slave;
  input            cpu_data_master_qualified_request_sysid_control_slave;
  input            cpu_data_master_qualified_request_timer_s1;
  input            cpu_data_master_read;
  input            cpu_data_master_read_data_valid_Din_s1;
  input            cpu_data_master_read_data_valid_Dout_s1;
  input            cpu_data_master_read_data_valid_SEG_H_s1;
  input            cpu_data_master_read_data_valid_SEG_l_s1;
  input            cpu_data_master_read_data_valid_addr_s1;
  input            cpu_data_master_read_data_valid_character_lcd_0_avalon_lcd_slave;
  input            cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  input            cpu_data_master_read_data_valid_flash_s1;
  input            cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_read_data_valid_nCS_s1;
  input            cpu_data_master_read_data_valid_nRD_s1;
  input            cpu_data_master_read_data_valid_nWR_s1;
  input            cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave;
  input            cpu_data_master_read_data_valid_sram_0_avalon_sram_slave;
  input            cpu_data_master_read_data_valid_sysid_control_slave;
  input            cpu_data_master_read_data_valid_timer_s1;
  input            cpu_data_master_requests_Din_s1;
  input            cpu_data_master_requests_Dout_s1;
  input            cpu_data_master_requests_SEG_H_s1;
  input            cpu_data_master_requests_SEG_l_s1;
  input            cpu_data_master_requests_addr_s1;
  input            cpu_data_master_requests_character_lcd_0_avalon_lcd_slave;
  input            cpu_data_master_requests_cpu_jtag_debug_module;
  input            cpu_data_master_requests_flash_s1;
  input            cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  input            cpu_data_master_requests_nCS_s1;
  input            cpu_data_master_requests_nRD_s1;
  input            cpu_data_master_requests_nWR_s1;
  input            cpu_data_master_requests_ps2_0_avalon_PS2_slave;
  input            cpu_data_master_requests_sram_0_avalon_sram_slave;
  input            cpu_data_master_requests_sysid_control_slave;
  input            cpu_data_master_requests_timer_s1;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input   [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  input            d1_Din_s1_end_xfer;
  input            d1_Dout_s1_end_xfer;
  input            d1_SEG_H_s1_end_xfer;
  input            d1_SEG_l_s1_end_xfer;
  input            d1_addr_s1_end_xfer;
  input            d1_character_lcd_0_avalon_lcd_slave_end_xfer;
  input            d1_cpu_jtag_debug_module_end_xfer;
  input            d1_jtag_uart_avalon_jtag_slave_end_xfer;
  input            d1_nCS_s1_end_xfer;
  input            d1_nRD_s1_end_xfer;
  input            d1_nWR_s1_end_xfer;
  input            d1_ps2_0_avalon_PS2_slave_end_xfer;
  input            d1_sram_0_avalon_sram_slave_end_xfer;
  input            d1_sysid_control_slave_end_xfer;
  input            d1_timer_s1_end_xfer;
  input            d1_tristate_bridge_avalon_slave_end_xfer;
  input   [  7: 0] incoming_data_to_and_from_the_flash_with_Xs_converted_to_0;
  input            jtag_uart_avalon_jtag_slave_irq_from_sa;
  input   [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  input            jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  input            ps2_0_avalon_PS2_slave_irq_from_sa;
  input   [ 31: 0] ps2_0_avalon_PS2_slave_readdata_from_sa;
  input            ps2_0_avalon_PS2_slave_waitrequest_from_sa;
  input            registered_cpu_data_master_read_data_valid_flash_s1;
  input            registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave;
  input            registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave;
  input            reset_n;
  input   [ 15: 0] sram_0_avalon_sram_slave_readdata_from_sa;
  input   [ 31: 0] sysid_control_slave_readdata_from_sa;
  input            timer_s1_irq_from_sa;
  input   [ 15: 0] timer_s1_readdata_from_sa;

  wire    [ 23: 0] cpu_data_master_address_to_slave;
  reg     [  1: 0] cpu_data_master_dbs_address;
  wire    [  1: 0] cpu_data_master_dbs_increment;
  wire    [ 15: 0] cpu_data_master_dbs_write_16;
  wire    [  7: 0] cpu_data_master_dbs_write_8;
  wire    [ 31: 0] cpu_data_master_irq;
  reg              cpu_data_master_no_byte_enables_and_last_term;
  wire    [ 31: 0] cpu_data_master_readdata;
  wire             cpu_data_master_run;
  reg              cpu_data_master_waitrequest;
  reg     [ 15: 0] dbs_16_reg_segment_0;
  reg     [  7: 0] dbs_8_reg_segment_0;
  reg     [  7: 0] dbs_8_reg_segment_1;
  reg     [  7: 0] dbs_8_reg_segment_2;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  wire             last_dbs_term_and_run;
  wire    [  1: 0] next_dbs_address;
  wire    [ 15: 0] p1_dbs_16_reg_segment_0;
  wire    [  7: 0] p1_dbs_8_reg_segment_0;
  wire    [  7: 0] p1_dbs_8_reg_segment_1;
  wire    [  7: 0] p1_dbs_8_reg_segment_2;
  wire    [ 31: 0] p1_registered_cpu_data_master_readdata;
  wire             pre_dbs_count_enable;
  wire             r_0;
  wire             r_1;
  wire             r_2;
  wire             r_3;
  reg     [ 31: 0] registered_cpu_data_master_readdata;
  //r_0 master_run cascaded wait assignment, which is an e_assign
  assign r_0 = 1 & ((~cpu_data_master_qualified_request_Din_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_Din_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_Dout_s1 | ~cpu_data_master_requests_Dout_s1) & ((~cpu_data_master_qualified_request_Dout_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_Dout_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_SEG_H_s1 | ~cpu_data_master_requests_SEG_H_s1) & ((~cpu_data_master_qualified_request_SEG_H_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_SEG_H_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_SEG_l_s1 | ~cpu_data_master_requests_SEG_l_s1) & ((~cpu_data_master_qualified_request_SEG_l_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_SEG_l_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_addr_s1 | ~cpu_data_master_requests_addr_s1) & ((~cpu_data_master_qualified_request_addr_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_addr_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1;

  //cascaded wait assignment, which is an e_assign
  assign cpu_data_master_run = r_0 & r_1 & r_2 & r_3;

  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = (cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave | ~cpu_data_master_requests_character_lcd_0_avalon_lcd_slave) & ((~cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~character_lcd_0_avalon_lcd_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~character_lcd_0_avalon_lcd_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_requests_cpu_jtag_debug_module) & (cpu_data_master_granted_cpu_jtag_debug_module | ~cpu_data_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_cpu_jtag_debug_module | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~cpu_data_master_requests_jtag_uart_avalon_jtag_slave) & ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & ((~cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~jtag_uart_avalon_jtag_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_nCS_s1 | ~cpu_data_master_requests_nCS_s1) & ((~cpu_data_master_qualified_request_nCS_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_nCS_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_nRD_s1 | ~cpu_data_master_requests_nRD_s1) & ((~cpu_data_master_qualified_request_nRD_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_nRD_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write)));

  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = 1 & (cpu_data_master_qualified_request_nWR_s1 | ~cpu_data_master_requests_nWR_s1) & ((~cpu_data_master_qualified_request_nWR_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_nWR_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave | registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave | ~cpu_data_master_requests_ps2_0_avalon_PS2_slave) & ((~cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave | ~cpu_data_master_read | (registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave | ~(cpu_data_master_read | cpu_data_master_write) | (1 & ~ps2_0_avalon_PS2_slave_waitrequest_from_sa & (cpu_data_master_read | cpu_data_master_write)))) & 1 & (cpu_data_master_qualified_request_sram_0_avalon_sram_slave | (registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave & cpu_data_master_dbs_address[1]) | (cpu_data_master_write & !cpu_data_master_byteenable_sram_0_avalon_sram_slave & cpu_data_master_dbs_address[1]) | ~cpu_data_master_requests_sram_0_avalon_sram_slave) & (cpu_data_master_granted_sram_0_avalon_sram_slave | ~cpu_data_master_qualified_request_sram_0_avalon_sram_slave) & ((~cpu_data_master_qualified_request_sram_0_avalon_sram_slave | ~cpu_data_master_read | (registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave & (cpu_data_master_dbs_address[1]) & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_sram_0_avalon_sram_slave | ~cpu_data_master_write | (1 & (cpu_data_master_dbs_address[1]) & cpu_data_master_write))) & 1 & ((~cpu_data_master_qualified_request_sysid_control_slave | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_sysid_control_slave | ~cpu_data_master_write | (1 & cpu_data_master_write))) & 1 & (cpu_data_master_qualified_request_timer_s1 | ~cpu_data_master_requests_timer_s1) & ((~cpu_data_master_qualified_request_timer_s1 | ~cpu_data_master_read | (1 & 1 & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_timer_s1 | ~cpu_data_master_write | (1 & cpu_data_master_write)));

  //r_3 master_run cascaded wait assignment, which is an e_assign
  assign r_3 = 1 & ((cpu_data_master_qualified_request_flash_s1 | (registered_cpu_data_master_read_data_valid_flash_s1 & cpu_data_master_dbs_address[1] & cpu_data_master_dbs_address[0]) | ((cpu_data_master_write & !cpu_data_master_byteenable_flash_s1 & cpu_data_master_dbs_address[1] & cpu_data_master_dbs_address[0])) | ~cpu_data_master_requests_flash_s1)) & (cpu_data_master_granted_flash_s1 | ~cpu_data_master_qualified_request_flash_s1) & ((~cpu_data_master_qualified_request_flash_s1 | ~cpu_data_master_read | (registered_cpu_data_master_read_data_valid_flash_s1 & (cpu_data_master_dbs_address[1] & cpu_data_master_dbs_address[0]) & cpu_data_master_read))) & ((~cpu_data_master_qualified_request_flash_s1 | ~cpu_data_master_write | (1 & (cpu_data_master_dbs_address[1] & cpu_data_master_dbs_address[0]) & cpu_data_master_write)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_data_master_address_to_slave = {cpu_data_master_address[23],
    1'b0,
    cpu_data_master_address[21 : 0]};

  //cpu/data_master readdata mux, which is an e_mux
  assign cpu_data_master_readdata = ({32 {~cpu_data_master_requests_Din_s1}} | Din_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_character_lcd_0_avalon_lcd_slave}} | registered_cpu_data_master_readdata) &
    ({32 {~cpu_data_master_requests_cpu_jtag_debug_module}} | cpu_jtag_debug_module_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_jtag_uart_avalon_jtag_slave}} | registered_cpu_data_master_readdata) &
    ({32 {~cpu_data_master_requests_ps2_0_avalon_PS2_slave}} | ps2_0_avalon_PS2_slave_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_sram_0_avalon_sram_slave}} | {sram_0_avalon_sram_slave_readdata_from_sa[15 : 0],
    dbs_16_reg_segment_0}) &
    ({32 {~cpu_data_master_requests_sysid_control_slave}} | sysid_control_slave_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_timer_s1}} | timer_s1_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_flash_s1}} | {incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[7 : 0],
    dbs_8_reg_segment_2,
    dbs_8_reg_segment_1,
    dbs_8_reg_segment_0});

  //actual waitrequest port, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_waitrequest <= ~0;
      else if (1)
          cpu_data_master_waitrequest <= ~((~(cpu_data_master_read | cpu_data_master_write))? 0: (cpu_data_master_run & cpu_data_master_waitrequest));
    end


  //unpredictable registered wait state incoming data, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          registered_cpu_data_master_readdata <= 0;
      else if (1)
          registered_cpu_data_master_readdata <= p1_registered_cpu_data_master_readdata;
    end


  //registered readdata mux, which is an e_mux
  assign p1_registered_cpu_data_master_readdata = ({32 {~cpu_data_master_requests_character_lcd_0_avalon_lcd_slave}} | character_lcd_0_avalon_lcd_slave_readdata_from_sa) &
    ({32 {~cpu_data_master_requests_jtag_uart_avalon_jtag_slave}} | jtag_uart_avalon_jtag_slave_readdata_from_sa);

  //irq assign, which is an e_assign
  assign cpu_data_master_irq = {1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    1'b0,
    ps2_0_avalon_PS2_slave_irq_from_sa,
    timer_s1_irq_from_sa,
    jtag_uart_avalon_jtag_slave_irq_from_sa};

  //no_byte_enables_and_last_term, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_no_byte_enables_and_last_term <= 0;
      else if (1)
          cpu_data_master_no_byte_enables_and_last_term <= last_dbs_term_and_run;
    end


  //compute the last dbs term, which is an e_mux
  assign last_dbs_term_and_run = (cpu_data_master_requests_sram_0_avalon_sram_slave)? (((cpu_data_master_dbs_address == 2'b10) & cpu_data_master_write & !cpu_data_master_byteenable_sram_0_avalon_sram_slave)) :
    (((cpu_data_master_dbs_address == 2'b11) & cpu_data_master_write & !cpu_data_master_byteenable_flash_s1));

  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = (((~cpu_data_master_no_byte_enables_and_last_term) & cpu_data_master_requests_sram_0_avalon_sram_slave & cpu_data_master_write & !cpu_data_master_byteenable_sram_0_avalon_sram_slave)) |
    cpu_data_master_read_data_valid_sram_0_avalon_sram_slave |
    (cpu_data_master_granted_sram_0_avalon_sram_slave & cpu_data_master_write & 1 & 1) |
    (((~cpu_data_master_no_byte_enables_and_last_term) & cpu_data_master_requests_flash_s1 & cpu_data_master_write & !cpu_data_master_byteenable_flash_s1)) |
    cpu_data_master_read_data_valid_flash_s1 |
    (cpu_data_master_granted_flash_s1 & cpu_data_master_write & 1 & 1);

  //input to dbs-16 stored 0, which is an e_mux
  assign p1_dbs_16_reg_segment_0 = sram_0_avalon_sram_slave_readdata_from_sa;

  //dbs register for dbs-16 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_16_reg_segment_0 <= 0;
      else if (dbs_count_enable & ((cpu_data_master_dbs_address[1]) == 0))
          dbs_16_reg_segment_0 <= p1_dbs_16_reg_segment_0;
    end


  //mux write dbs 1, which is an e_mux
  assign cpu_data_master_dbs_write_16 = (cpu_data_master_dbs_address[1])? cpu_data_master_writedata[31 : 16] :
    cpu_data_master_writedata[15 : 0];

  //dbs count increment, which is an e_mux
  assign cpu_data_master_dbs_increment = (cpu_data_master_requests_sram_0_avalon_sram_slave)? 2 :
    (cpu_data_master_requests_flash_s1)? 1 :
    0;

  //dbs counter overflow, which is an e_assign
  assign dbs_counter_overflow = cpu_data_master_dbs_address[1] & !(next_dbs_address[1]);

  //next master address, which is an e_assign
  assign next_dbs_address = cpu_data_master_dbs_address + cpu_data_master_dbs_increment;

  //dbs count enable, which is an e_mux
  assign dbs_count_enable = pre_dbs_count_enable &
    (~(cpu_data_master_requests_sram_0_avalon_sram_slave & ~cpu_data_master_waitrequest & cpu_data_master_write)) &
    (~(cpu_data_master_requests_flash_s1 & ~cpu_data_master_waitrequest & cpu_data_master_write));

  //dbs counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_dbs_address <= 0;
      else if (dbs_count_enable)
          cpu_data_master_dbs_address <= next_dbs_address;
    end


  //input to dbs-8 stored 0, which is an e_mux
  assign p1_dbs_8_reg_segment_0 = incoming_data_to_and_from_the_flash_with_Xs_converted_to_0;

  //dbs register for dbs-8 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_8_reg_segment_0 <= 0;
      else if (dbs_count_enable & ((cpu_data_master_dbs_address[1 : 0]) == 0))
          dbs_8_reg_segment_0 <= p1_dbs_8_reg_segment_0;
    end


  //input to dbs-8 stored 1, which is an e_mux
  assign p1_dbs_8_reg_segment_1 = incoming_data_to_and_from_the_flash_with_Xs_converted_to_0;

  //dbs register for dbs-8 segment 1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_8_reg_segment_1 <= 0;
      else if (dbs_count_enable & ((cpu_data_master_dbs_address[1 : 0]) == 1))
          dbs_8_reg_segment_1 <= p1_dbs_8_reg_segment_1;
    end


  //input to dbs-8 stored 2, which is an e_mux
  assign p1_dbs_8_reg_segment_2 = incoming_data_to_and_from_the_flash_with_Xs_converted_to_0;

  //dbs register for dbs-8 segment 2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_8_reg_segment_2 <= 0;
      else if (dbs_count_enable & ((cpu_data_master_dbs_address[1 : 0]) == 2))
          dbs_8_reg_segment_2 <= p1_dbs_8_reg_segment_2;
    end


  //mux write dbs 2, which is an e_mux
  assign cpu_data_master_dbs_write_8 = ((cpu_data_master_dbs_address[1 : 0] == 0))? cpu_data_master_writedata[7 : 0] :
    ((cpu_data_master_dbs_address[1 : 0] == 1))? cpu_data_master_writedata[15 : 8] :
    ((cpu_data_master_dbs_address[1 : 0] == 2))? cpu_data_master_writedata[23 : 16] :
    cpu_data_master_writedata[31 : 24];


endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module cpu_instruction_master_arbitrator (
                                           // inputs:
                                            clk,
                                            cpu_instruction_master_address,
                                            cpu_instruction_master_granted_cpu_jtag_debug_module,
                                            cpu_instruction_master_granted_flash_s1,
                                            cpu_instruction_master_granted_sram_0_avalon_sram_slave,
                                            cpu_instruction_master_qualified_request_cpu_jtag_debug_module,
                                            cpu_instruction_master_qualified_request_flash_s1,
                                            cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave,
                                            cpu_instruction_master_read,
                                            cpu_instruction_master_read_data_valid_cpu_jtag_debug_module,
                                            cpu_instruction_master_read_data_valid_flash_s1,
                                            cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave,
                                            cpu_instruction_master_requests_cpu_jtag_debug_module,
                                            cpu_instruction_master_requests_flash_s1,
                                            cpu_instruction_master_requests_sram_0_avalon_sram_slave,
                                            cpu_jtag_debug_module_readdata_from_sa,
                                            d1_cpu_jtag_debug_module_end_xfer,
                                            d1_sram_0_avalon_sram_slave_end_xfer,
                                            d1_tristate_bridge_avalon_slave_end_xfer,
                                            incoming_data_to_and_from_the_flash,
                                            reset_n,
                                            sram_0_avalon_sram_slave_readdata_from_sa,

                                           // outputs:
                                            cpu_instruction_master_address_to_slave,
                                            cpu_instruction_master_dbs_address,
                                            cpu_instruction_master_latency_counter,
                                            cpu_instruction_master_readdata,
                                            cpu_instruction_master_readdatavalid,
                                            cpu_instruction_master_waitrequest
                                         )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [ 23: 0] cpu_instruction_master_address_to_slave;
  output  [  1: 0] cpu_instruction_master_dbs_address;
  output  [  1: 0] cpu_instruction_master_latency_counter;
  output  [ 31: 0] cpu_instruction_master_readdata;
  output           cpu_instruction_master_readdatavalid;
  output           cpu_instruction_master_waitrequest;
  input            clk;
  input   [ 23: 0] cpu_instruction_master_address;
  input            cpu_instruction_master_granted_cpu_jtag_debug_module;
  input            cpu_instruction_master_granted_flash_s1;
  input            cpu_instruction_master_granted_sram_0_avalon_sram_slave;
  input            cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  input            cpu_instruction_master_qualified_request_flash_s1;
  input            cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave;
  input            cpu_instruction_master_read;
  input            cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  input            cpu_instruction_master_read_data_valid_flash_s1;
  input            cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave;
  input            cpu_instruction_master_requests_cpu_jtag_debug_module;
  input            cpu_instruction_master_requests_flash_s1;
  input            cpu_instruction_master_requests_sram_0_avalon_sram_slave;
  input   [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  input            d1_cpu_jtag_debug_module_end_xfer;
  input            d1_sram_0_avalon_sram_slave_end_xfer;
  input            d1_tristate_bridge_avalon_slave_end_xfer;
  input   [  7: 0] incoming_data_to_and_from_the_flash;
  input            reset_n;
  input   [ 15: 0] sram_0_avalon_sram_slave_readdata_from_sa;

  reg              active_and_waiting_last_time;
  reg     [ 23: 0] cpu_instruction_master_address_last_time;
  wire    [ 23: 0] cpu_instruction_master_address_to_slave;
  reg     [  1: 0] cpu_instruction_master_dbs_address;
  wire    [  1: 0] cpu_instruction_master_dbs_increment;
  reg     [  1: 0] cpu_instruction_master_dbs_rdv_counter;
  wire    [  1: 0] cpu_instruction_master_dbs_rdv_counter_inc;
  wire             cpu_instruction_master_is_granted_some_slave;
  reg     [  1: 0] cpu_instruction_master_latency_counter;
  wire    [  1: 0] cpu_instruction_master_next_dbs_rdv_counter;
  reg              cpu_instruction_master_read_but_no_slave_selected;
  reg              cpu_instruction_master_read_last_time;
  wire    [ 31: 0] cpu_instruction_master_readdata;
  wire             cpu_instruction_master_readdatavalid;
  wire             cpu_instruction_master_run;
  wire             cpu_instruction_master_waitrequest;
  wire             dbs_count_enable;
  wire             dbs_counter_overflow;
  reg     [ 15: 0] dbs_latent_16_reg_segment_0;
  reg     [  7: 0] dbs_latent_8_reg_segment_0;
  reg     [  7: 0] dbs_latent_8_reg_segment_1;
  reg     [  7: 0] dbs_latent_8_reg_segment_2;
  wire             dbs_rdv_count_enable;
  wire             dbs_rdv_counter_overflow;
  wire    [  1: 0] latency_load_value;
  wire    [  1: 0] next_dbs_address;
  wire    [  1: 0] p1_cpu_instruction_master_latency_counter;
  wire    [ 15: 0] p1_dbs_latent_16_reg_segment_0;
  wire    [  7: 0] p1_dbs_latent_8_reg_segment_0;
  wire    [  7: 0] p1_dbs_latent_8_reg_segment_1;
  wire    [  7: 0] p1_dbs_latent_8_reg_segment_2;
  wire             pre_dbs_count_enable;
  wire             pre_flush_cpu_instruction_master_readdatavalid;
  wire             r_1;
  wire             r_2;
  wire             r_3;
  //r_1 master_run cascaded wait assignment, which is an e_assign
  assign r_1 = 1 & (cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~cpu_instruction_master_requests_cpu_jtag_debug_module) & (cpu_instruction_master_granted_cpu_jtag_debug_module | ~cpu_instruction_master_qualified_request_cpu_jtag_debug_module) & ((~cpu_instruction_master_qualified_request_cpu_jtag_debug_module | ~cpu_instruction_master_read | (1 & ~d1_cpu_jtag_debug_module_end_xfer & cpu_instruction_master_read)));

  //cascaded wait assignment, which is an e_assign
  assign cpu_instruction_master_run = r_1 & r_2 & r_3;

  //r_2 master_run cascaded wait assignment, which is an e_assign
  assign r_2 = 1 & (cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave | ~cpu_instruction_master_requests_sram_0_avalon_sram_slave) & (cpu_instruction_master_granted_sram_0_avalon_sram_slave | ~cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave) & ((~cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave | ~cpu_instruction_master_read | (1 & (cpu_instruction_master_dbs_address[1]) & cpu_instruction_master_read)));

  //r_3 master_run cascaded wait assignment, which is an e_assign
  assign r_3 = 1 & (cpu_instruction_master_qualified_request_flash_s1 | ~cpu_instruction_master_requests_flash_s1) & (cpu_instruction_master_granted_flash_s1 | ~cpu_instruction_master_qualified_request_flash_s1) & ((~cpu_instruction_master_qualified_request_flash_s1 | ~cpu_instruction_master_read | (1 & (cpu_instruction_master_dbs_address[1] & cpu_instruction_master_dbs_address[0]) & cpu_instruction_master_read)));

  //optimize select-logic by passing only those address bits which matter.
  assign cpu_instruction_master_address_to_slave = {cpu_instruction_master_address[23],
    1'b0,
    cpu_instruction_master_address[21 : 0]};

  //cpu_instruction_master_read_but_no_slave_selected assignment, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_read_but_no_slave_selected <= 0;
      else if (1)
          cpu_instruction_master_read_but_no_slave_selected <= cpu_instruction_master_read & cpu_instruction_master_run & ~cpu_instruction_master_is_granted_some_slave;
    end


  //some slave is getting selected, which is an e_mux
  assign cpu_instruction_master_is_granted_some_slave = cpu_instruction_master_granted_cpu_jtag_debug_module |
    cpu_instruction_master_granted_sram_0_avalon_sram_slave |
    cpu_instruction_master_granted_flash_s1;

  //latent slave read data valids which may be flushed, which is an e_mux
  assign pre_flush_cpu_instruction_master_readdatavalid = (cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave & dbs_rdv_counter_overflow) |
    (cpu_instruction_master_read_data_valid_flash_s1 & dbs_rdv_counter_overflow);

  //latent slave read data valid which is not flushed, which is an e_mux
  assign cpu_instruction_master_readdatavalid = cpu_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_instruction_master_readdatavalid |
    cpu_instruction_master_read_data_valid_cpu_jtag_debug_module |
    cpu_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_instruction_master_readdatavalid |
    cpu_instruction_master_read_but_no_slave_selected |
    pre_flush_cpu_instruction_master_readdatavalid;

  //cpu/instruction_master readdata mux, which is an e_mux
  assign cpu_instruction_master_readdata = ({32 {~(cpu_instruction_master_qualified_request_cpu_jtag_debug_module & cpu_instruction_master_read)}} | cpu_jtag_debug_module_readdata_from_sa) &
    ({32 {~cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave}} | {sram_0_avalon_sram_slave_readdata_from_sa[15 : 0],
    dbs_latent_16_reg_segment_0}) &
    ({32 {~cpu_instruction_master_read_data_valid_flash_s1}} | {incoming_data_to_and_from_the_flash[7 : 0],
    dbs_latent_8_reg_segment_2,
    dbs_latent_8_reg_segment_1,
    dbs_latent_8_reg_segment_0});

  //actual waitrequest port, which is an e_assign
  assign cpu_instruction_master_waitrequest = ~cpu_instruction_master_run;

  //latent max counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_latency_counter <= 0;
      else if (1)
          cpu_instruction_master_latency_counter <= p1_cpu_instruction_master_latency_counter;
    end


  //latency counter load mux, which is an e_mux
  assign p1_cpu_instruction_master_latency_counter = ((cpu_instruction_master_run & cpu_instruction_master_read))? latency_load_value :
    (cpu_instruction_master_latency_counter)? cpu_instruction_master_latency_counter - 1 :
    0;

  //read latency load values, which is an e_mux
  assign latency_load_value = ({2 {cpu_instruction_master_requests_sram_0_avalon_sram_slave}} & 2) |
    ({2 {cpu_instruction_master_requests_flash_s1}} & 2);

  //input to latent dbs-16 stored 0, which is an e_mux
  assign p1_dbs_latent_16_reg_segment_0 = sram_0_avalon_sram_slave_readdata_from_sa;

  //dbs register for latent dbs-16 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_16_reg_segment_0 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_instruction_master_dbs_rdv_counter[1]) == 0))
          dbs_latent_16_reg_segment_0 <= p1_dbs_latent_16_reg_segment_0;
    end


  //dbs count increment, which is an e_mux
  assign cpu_instruction_master_dbs_increment = (cpu_instruction_master_requests_sram_0_avalon_sram_slave)? 2 :
    (cpu_instruction_master_requests_flash_s1)? 1 :
    0;

  //dbs counter overflow, which is an e_assign
  assign dbs_counter_overflow = cpu_instruction_master_dbs_address[1] & !(next_dbs_address[1]);

  //next master address, which is an e_assign
  assign next_dbs_address = cpu_instruction_master_dbs_address + cpu_instruction_master_dbs_increment;

  //dbs count enable, which is an e_mux
  assign dbs_count_enable = pre_dbs_count_enable;

  //dbs counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_dbs_address <= 0;
      else if (dbs_count_enable)
          cpu_instruction_master_dbs_address <= next_dbs_address;
    end


  //p1 dbs rdv counter, which is an e_assign
  assign cpu_instruction_master_next_dbs_rdv_counter = cpu_instruction_master_dbs_rdv_counter + cpu_instruction_master_dbs_rdv_counter_inc;

  //cpu_instruction_master_rdv_inc_mux, which is an e_mux
  assign cpu_instruction_master_dbs_rdv_counter_inc = (cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave)? 2 :
    1;

  //master any slave rdv, which is an e_mux
  assign dbs_rdv_count_enable = cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave |
    cpu_instruction_master_read_data_valid_flash_s1;

  //dbs rdv counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_dbs_rdv_counter <= 0;
      else if (dbs_rdv_count_enable)
          cpu_instruction_master_dbs_rdv_counter <= cpu_instruction_master_next_dbs_rdv_counter;
    end


  //dbs rdv counter overflow, which is an e_assign
  assign dbs_rdv_counter_overflow = cpu_instruction_master_dbs_rdv_counter[1] & ~cpu_instruction_master_next_dbs_rdv_counter[1];

  //pre dbs count enable, which is an e_mux
  assign pre_dbs_count_enable = (cpu_instruction_master_granted_sram_0_avalon_sram_slave & cpu_instruction_master_read & 1 & 1) |
    (cpu_instruction_master_granted_flash_s1 & cpu_instruction_master_read & 1 & 1);

  //input to latent dbs-8 stored 0, which is an e_mux
  assign p1_dbs_latent_8_reg_segment_0 = incoming_data_to_and_from_the_flash;

  //dbs register for latent dbs-8 segment 0, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_8_reg_segment_0 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_instruction_master_dbs_rdv_counter[1 : 0]) == 0))
          dbs_latent_8_reg_segment_0 <= p1_dbs_latent_8_reg_segment_0;
    end


  //input to latent dbs-8 stored 1, which is an e_mux
  assign p1_dbs_latent_8_reg_segment_1 = incoming_data_to_and_from_the_flash;

  //dbs register for latent dbs-8 segment 1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_8_reg_segment_1 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_instruction_master_dbs_rdv_counter[1 : 0]) == 1))
          dbs_latent_8_reg_segment_1 <= p1_dbs_latent_8_reg_segment_1;
    end


  //input to latent dbs-8 stored 2, which is an e_mux
  assign p1_dbs_latent_8_reg_segment_2 = incoming_data_to_and_from_the_flash;

  //dbs register for latent dbs-8 segment 2, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          dbs_latent_8_reg_segment_2 <= 0;
      else if (dbs_rdv_count_enable & ((cpu_instruction_master_dbs_rdv_counter[1 : 0]) == 2))
          dbs_latent_8_reg_segment_2 <= p1_dbs_latent_8_reg_segment_2;
    end



//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //cpu_instruction_master_address check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_address_last_time <= 0;
      else if (1)
          cpu_instruction_master_address_last_time <= cpu_instruction_master_address;
    end


  //cpu/instruction_master waited last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          active_and_waiting_last_time <= 0;
      else if (1)
          active_and_waiting_last_time <= cpu_instruction_master_waitrequest & (cpu_instruction_master_read);
    end


  //cpu_instruction_master_address matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or cpu_instruction_master_address or cpu_instruction_master_address_last_time)
    begin
      if (active_and_waiting_last_time & (cpu_instruction_master_address != cpu_instruction_master_address_last_time))
        begin
          $write("%0d ns: cpu_instruction_master_address did not heed wait!!!", $time);
          $stop;
        end
    end


  //cpu_instruction_master_read check against wait, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_read_last_time <= 0;
      else if (1)
          cpu_instruction_master_read_last_time <= cpu_instruction_master_read;
    end


  //cpu_instruction_master_read matches last port_name, which is an e_process
  always @(active_and_waiting_last_time or cpu_instruction_master_read or cpu_instruction_master_read_last_time)
    begin
      if (active_and_waiting_last_time & (cpu_instruction_master_read != cpu_instruction_master_read_last_time))
        begin
          $write("%0d ns: cpu_instruction_master_read did not heed wait!!!", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module jtag_uart_avalon_jtag_slave_arbitrator (
                                                // inputs:
                                                 clk,
                                                 cpu_data_master_address_to_slave,
                                                 cpu_data_master_read,
                                                 cpu_data_master_waitrequest,
                                                 cpu_data_master_write,
                                                 cpu_data_master_writedata,
                                                 jtag_uart_avalon_jtag_slave_dataavailable,
                                                 jtag_uart_avalon_jtag_slave_irq,
                                                 jtag_uart_avalon_jtag_slave_readdata,
                                                 jtag_uart_avalon_jtag_slave_readyfordata,
                                                 jtag_uart_avalon_jtag_slave_waitrequest,
                                                 reset_n,

                                                // outputs:
                                                 cpu_data_master_granted_jtag_uart_avalon_jtag_slave,
                                                 cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave,
                                                 cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave,
                                                 cpu_data_master_requests_jtag_uart_avalon_jtag_slave,
                                                 d1_jtag_uart_avalon_jtag_slave_end_xfer,
                                                 jtag_uart_avalon_jtag_slave_address,
                                                 jtag_uart_avalon_jtag_slave_chipselect,
                                                 jtag_uart_avalon_jtag_slave_dataavailable_from_sa,
                                                 jtag_uart_avalon_jtag_slave_irq_from_sa,
                                                 jtag_uart_avalon_jtag_slave_read_n,
                                                 jtag_uart_avalon_jtag_slave_readdata_from_sa,
                                                 jtag_uart_avalon_jtag_slave_readyfordata_from_sa,
                                                 jtag_uart_avalon_jtag_slave_reset_n,
                                                 jtag_uart_avalon_jtag_slave_waitrequest_from_sa,
                                                 jtag_uart_avalon_jtag_slave_write_n,
                                                 jtag_uart_avalon_jtag_slave_writedata
                                              )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output           cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  output           cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  output           cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  output           cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  output           d1_jtag_uart_avalon_jtag_slave_end_xfer;
  output           jtag_uart_avalon_jtag_slave_address;
  output           jtag_uart_avalon_jtag_slave_chipselect;
  output           jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  output           jtag_uart_avalon_jtag_slave_irq_from_sa;
  output           jtag_uart_avalon_jtag_slave_read_n;
  output  [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  output           jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  output           jtag_uart_avalon_jtag_slave_reset_n;
  output           jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  output           jtag_uart_avalon_jtag_slave_write_n;
  output  [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            jtag_uart_avalon_jtag_slave_dataavailable;
  input            jtag_uart_avalon_jtag_slave_irq;
  input   [ 31: 0] jtag_uart_avalon_jtag_slave_readdata;
  input            jtag_uart_avalon_jtag_slave_readyfordata;
  input            jtag_uart_avalon_jtag_slave_waitrequest;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_saved_grant_jtag_uart_avalon_jtag_slave;
  reg              d1_jtag_uart_avalon_jtag_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             jtag_uart_avalon_jtag_slave_address;
  wire             jtag_uart_avalon_jtag_slave_allgrants;
  wire             jtag_uart_avalon_jtag_slave_allow_new_arb_cycle;
  wire             jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant;
  wire             jtag_uart_avalon_jtag_slave_any_continuerequest;
  wire             jtag_uart_avalon_jtag_slave_arb_counter_enable;
  reg     [  2: 0] jtag_uart_avalon_jtag_slave_arb_share_counter;
  wire    [  2: 0] jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
  wire    [  2: 0] jtag_uart_avalon_jtag_slave_arb_share_set_values;
  wire             jtag_uart_avalon_jtag_slave_beginbursttransfer_internal;
  wire             jtag_uart_avalon_jtag_slave_begins_xfer;
  wire             jtag_uart_avalon_jtag_slave_chipselect;
  wire             jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_avalon_jtag_slave_end_xfer;
  wire             jtag_uart_avalon_jtag_slave_firsttransfer;
  wire             jtag_uart_avalon_jtag_slave_grant_vector;
  wire             jtag_uart_avalon_jtag_slave_in_a_read_cycle;
  wire             jtag_uart_avalon_jtag_slave_in_a_write_cycle;
  wire             jtag_uart_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_avalon_jtag_slave_master_qreq_vector;
  wire             jtag_uart_avalon_jtag_slave_non_bursting_master_requests;
  wire             jtag_uart_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  reg              jtag_uart_avalon_jtag_slave_reg_firsttransfer;
  wire             jtag_uart_avalon_jtag_slave_reset_n;
  reg              jtag_uart_avalon_jtag_slave_slavearbiterlockenable;
  wire             jtag_uart_avalon_jtag_slave_slavearbiterlockenable2;
  wire             jtag_uart_avalon_jtag_slave_unreg_firsttransfer;
  wire             jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_avalon_jtag_slave_waits_for_read;
  wire             jtag_uart_avalon_jtag_slave_waits_for_write;
  wire             jtag_uart_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
  wire    [ 23: 0] shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master;
  wire             wait_for_jtag_uart_avalon_jtag_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~jtag_uart_avalon_jtag_slave_end_xfer;
    end


  assign jtag_uart_avalon_jtag_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave));
  //assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_readdata_from_sa = jtag_uart_avalon_jtag_slave_readdata;

  assign cpu_data_master_requests_jtag_uart_avalon_jtag_slave = ({cpu_data_master_address_to_slave[23 : 3] , 3'b0} == 24'h810a0) & (cpu_data_master_read | cpu_data_master_write);
  //assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_dataavailable_from_sa = jtag_uart_avalon_jtag_slave_dataavailable;

  //assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_readyfordata_from_sa = jtag_uart_avalon_jtag_slave_readyfordata;

  //assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_waitrequest_from_sa = jtag_uart_avalon_jtag_slave_waitrequest;

  //jtag_uart_avalon_jtag_slave_arb_share_counter set values, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_arb_share_set_values = 1;

  //jtag_uart_avalon_jtag_slave_non_bursting_master_requests mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_non_bursting_master_requests = cpu_data_master_requests_jtag_uart_avalon_jtag_slave;

  //jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant = 0;

  //jtag_uart_avalon_jtag_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_arb_share_counter_next_value = jtag_uart_avalon_jtag_slave_firsttransfer ? (jtag_uart_avalon_jtag_slave_arb_share_set_values - 1) : |jtag_uart_avalon_jtag_slave_arb_share_counter ? (jtag_uart_avalon_jtag_slave_arb_share_counter - 1) : 0;

  //jtag_uart_avalon_jtag_slave_allgrants all slave grants, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_allgrants = |jtag_uart_avalon_jtag_slave_grant_vector;

  //jtag_uart_avalon_jtag_slave_end_xfer assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_end_xfer = ~(jtag_uart_avalon_jtag_slave_waits_for_read | jtag_uart_avalon_jtag_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave = jtag_uart_avalon_jtag_slave_end_xfer & (~jtag_uart_avalon_jtag_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //jtag_uart_avalon_jtag_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & jtag_uart_avalon_jtag_slave_allgrants) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests);

  //jtag_uart_avalon_jtag_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_avalon_jtag_slave_arb_share_counter <= 0;
      else if (jtag_uart_avalon_jtag_slave_arb_counter_enable)
          jtag_uart_avalon_jtag_slave_arb_share_counter <= jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //jtag_uart_avalon_jtag_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= 0;
      else if ((|jtag_uart_avalon_jtag_slave_master_qreq_vector & end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave) | (end_xfer_arb_share_counter_term_jtag_uart_avalon_jtag_slave & ~jtag_uart_avalon_jtag_slave_non_bursting_master_requests))
          jtag_uart_avalon_jtag_slave_slavearbiterlockenable <= |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;
    end


  //cpu/data_master jtag_uart/avalon_jtag_slave arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = jtag_uart_avalon_jtag_slave_slavearbiterlockenable & cpu_data_master_continuerequest;

  //jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 = |jtag_uart_avalon_jtag_slave_arb_share_counter_next_value;

  //cpu/data_master jtag_uart/avalon_jtag_slave arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = jtag_uart_avalon_jtag_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //jtag_uart_avalon_jtag_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave = cpu_data_master_requests_jtag_uart_avalon_jtag_slave & ~((cpu_data_master_read & (~cpu_data_master_waitrequest)) | ((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //jtag_uart_avalon_jtag_slave_writedata mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_jtag_uart_avalon_jtag_slave = cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;

  //cpu/data_master saved-grant jtag_uart/avalon_jtag_slave, which is an e_assign
  assign cpu_data_master_saved_grant_jtag_uart_avalon_jtag_slave = cpu_data_master_requests_jtag_uart_avalon_jtag_slave;

  //allow new arb cycle for jtag_uart/avalon_jtag_slave, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign jtag_uart_avalon_jtag_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign jtag_uart_avalon_jtag_slave_master_qreq_vector = 1;

  //jtag_uart_avalon_jtag_slave_reset_n assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_reset_n = reset_n;

  assign jtag_uart_avalon_jtag_slave_chipselect = cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  //jtag_uart_avalon_jtag_slave_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_firsttransfer = jtag_uart_avalon_jtag_slave_begins_xfer ? jtag_uart_avalon_jtag_slave_unreg_firsttransfer : jtag_uart_avalon_jtag_slave_reg_firsttransfer;

  //jtag_uart_avalon_jtag_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_unreg_firsttransfer = ~(jtag_uart_avalon_jtag_slave_slavearbiterlockenable & jtag_uart_avalon_jtag_slave_any_continuerequest);

  //jtag_uart_avalon_jtag_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          jtag_uart_avalon_jtag_slave_reg_firsttransfer <= 1'b1;
      else if (jtag_uart_avalon_jtag_slave_begins_xfer)
          jtag_uart_avalon_jtag_slave_reg_firsttransfer <= jtag_uart_avalon_jtag_slave_unreg_firsttransfer;
    end


  //jtag_uart_avalon_jtag_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_beginbursttransfer_internal = jtag_uart_avalon_jtag_slave_begins_xfer;

  //~jtag_uart_avalon_jtag_slave_read_n assignment, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_read_n = ~(cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read);

  //~jtag_uart_avalon_jtag_slave_write_n assignment, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_write_n = ~(cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_write);

  assign shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master = cpu_data_master_address_to_slave;
  //jtag_uart_avalon_jtag_slave_address mux, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_address = shifted_address_to_jtag_uart_avalon_jtag_slave_from_cpu_data_master >> 2;

  //d1_jtag_uart_avalon_jtag_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_jtag_uart_avalon_jtag_slave_end_xfer <= 1;
      else if (1)
          d1_jtag_uart_avalon_jtag_slave_end_xfer <= jtag_uart_avalon_jtag_slave_end_xfer;
    end


  //jtag_uart_avalon_jtag_slave_waits_for_read in a cycle, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_waits_for_read = jtag_uart_avalon_jtag_slave_in_a_read_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_avalon_jtag_slave_in_a_read_cycle assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_in_a_read_cycle = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = jtag_uart_avalon_jtag_slave_in_a_read_cycle;

  //jtag_uart_avalon_jtag_slave_waits_for_write in a cycle, which is an e_mux
  assign jtag_uart_avalon_jtag_slave_waits_for_write = jtag_uart_avalon_jtag_slave_in_a_write_cycle & jtag_uart_avalon_jtag_slave_waitrequest_from_sa;

  //jtag_uart_avalon_jtag_slave_in_a_write_cycle assignment, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_in_a_write_cycle = cpu_data_master_granted_jtag_uart_avalon_jtag_slave & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = jtag_uart_avalon_jtag_slave_in_a_write_cycle;

  assign wait_for_jtag_uart_avalon_jtag_slave_counter = 0;
  //assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign jtag_uart_avalon_jtag_slave_irq_from_sa = jtag_uart_avalon_jtag_slave_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //jtag_uart/avalon_jtag_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module nCS_s1_arbitrator (
                           // inputs:
                            clk,
                            cpu_data_master_address_to_slave,
                            cpu_data_master_read,
                            cpu_data_master_waitrequest,
                            cpu_data_master_write,
                            cpu_data_master_writedata,
                            reset_n,

                           // outputs:
                            cpu_data_master_granted_nCS_s1,
                            cpu_data_master_qualified_request_nCS_s1,
                            cpu_data_master_read_data_valid_nCS_s1,
                            cpu_data_master_requests_nCS_s1,
                            d1_nCS_s1_end_xfer,
                            nCS_s1_address,
                            nCS_s1_chipselect,
                            nCS_s1_reset_n,
                            nCS_s1_write_n,
                            nCS_s1_writedata
                         )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output           cpu_data_master_granted_nCS_s1;
  output           cpu_data_master_qualified_request_nCS_s1;
  output           cpu_data_master_read_data_valid_nCS_s1;
  output           cpu_data_master_requests_nCS_s1;
  output           d1_nCS_s1_end_xfer;
  output  [  1: 0] nCS_s1_address;
  output           nCS_s1_chipselect;
  output           nCS_s1_reset_n;
  output           nCS_s1_write_n;
  output           nCS_s1_writedata;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_nCS_s1;
  wire             cpu_data_master_qualified_request_nCS_s1;
  wire             cpu_data_master_read_data_valid_nCS_s1;
  wire             cpu_data_master_requests_nCS_s1;
  wire             cpu_data_master_saved_grant_nCS_s1;
  reg              d1_nCS_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_nCS_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] nCS_s1_address;
  wire             nCS_s1_allgrants;
  wire             nCS_s1_allow_new_arb_cycle;
  wire             nCS_s1_any_bursting_master_saved_grant;
  wire             nCS_s1_any_continuerequest;
  wire             nCS_s1_arb_counter_enable;
  reg     [  2: 0] nCS_s1_arb_share_counter;
  wire    [  2: 0] nCS_s1_arb_share_counter_next_value;
  wire    [  2: 0] nCS_s1_arb_share_set_values;
  wire             nCS_s1_beginbursttransfer_internal;
  wire             nCS_s1_begins_xfer;
  wire             nCS_s1_chipselect;
  wire             nCS_s1_end_xfer;
  wire             nCS_s1_firsttransfer;
  wire             nCS_s1_grant_vector;
  wire             nCS_s1_in_a_read_cycle;
  wire             nCS_s1_in_a_write_cycle;
  wire             nCS_s1_master_qreq_vector;
  wire             nCS_s1_non_bursting_master_requests;
  reg              nCS_s1_reg_firsttransfer;
  wire             nCS_s1_reset_n;
  reg              nCS_s1_slavearbiterlockenable;
  wire             nCS_s1_slavearbiterlockenable2;
  wire             nCS_s1_unreg_firsttransfer;
  wire             nCS_s1_waits_for_read;
  wire             nCS_s1_waits_for_write;
  wire             nCS_s1_write_n;
  wire             nCS_s1_writedata;
  wire    [ 23: 0] shifted_address_to_nCS_s1_from_cpu_data_master;
  wire             wait_for_nCS_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~nCS_s1_end_xfer;
    end


  assign nCS_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_nCS_s1));
  assign cpu_data_master_requests_nCS_s1 = (({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'h81020) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //nCS_s1_arb_share_counter set values, which is an e_mux
  assign nCS_s1_arb_share_set_values = 1;

  //nCS_s1_non_bursting_master_requests mux, which is an e_mux
  assign nCS_s1_non_bursting_master_requests = cpu_data_master_requests_nCS_s1;

  //nCS_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign nCS_s1_any_bursting_master_saved_grant = 0;

  //nCS_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign nCS_s1_arb_share_counter_next_value = nCS_s1_firsttransfer ? (nCS_s1_arb_share_set_values - 1) : |nCS_s1_arb_share_counter ? (nCS_s1_arb_share_counter - 1) : 0;

  //nCS_s1_allgrants all slave grants, which is an e_mux
  assign nCS_s1_allgrants = |nCS_s1_grant_vector;

  //nCS_s1_end_xfer assignment, which is an e_assign
  assign nCS_s1_end_xfer = ~(nCS_s1_waits_for_read | nCS_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_nCS_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_nCS_s1 = nCS_s1_end_xfer & (~nCS_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //nCS_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign nCS_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_nCS_s1 & nCS_s1_allgrants) | (end_xfer_arb_share_counter_term_nCS_s1 & ~nCS_s1_non_bursting_master_requests);

  //nCS_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nCS_s1_arb_share_counter <= 0;
      else if (nCS_s1_arb_counter_enable)
          nCS_s1_arb_share_counter <= nCS_s1_arb_share_counter_next_value;
    end


  //nCS_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nCS_s1_slavearbiterlockenable <= 0;
      else if ((|nCS_s1_master_qreq_vector & end_xfer_arb_share_counter_term_nCS_s1) | (end_xfer_arb_share_counter_term_nCS_s1 & ~nCS_s1_non_bursting_master_requests))
          nCS_s1_slavearbiterlockenable <= |nCS_s1_arb_share_counter_next_value;
    end


  //cpu/data_master nCS/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = nCS_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //nCS_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign nCS_s1_slavearbiterlockenable2 = |nCS_s1_arb_share_counter_next_value;

  //cpu/data_master nCS/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = nCS_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //nCS_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign nCS_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_nCS_s1 = cpu_data_master_requests_nCS_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //nCS_s1_writedata mux, which is an e_mux
  assign nCS_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_nCS_s1 = cpu_data_master_qualified_request_nCS_s1;

  //cpu/data_master saved-grant nCS/s1, which is an e_assign
  assign cpu_data_master_saved_grant_nCS_s1 = cpu_data_master_requests_nCS_s1;

  //allow new arb cycle for nCS/s1, which is an e_assign
  assign nCS_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign nCS_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign nCS_s1_master_qreq_vector = 1;

  //nCS_s1_reset_n assignment, which is an e_assign
  assign nCS_s1_reset_n = reset_n;

  assign nCS_s1_chipselect = cpu_data_master_granted_nCS_s1;
  //nCS_s1_firsttransfer first transaction, which is an e_assign
  assign nCS_s1_firsttransfer = nCS_s1_begins_xfer ? nCS_s1_unreg_firsttransfer : nCS_s1_reg_firsttransfer;

  //nCS_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign nCS_s1_unreg_firsttransfer = ~(nCS_s1_slavearbiterlockenable & nCS_s1_any_continuerequest);

  //nCS_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nCS_s1_reg_firsttransfer <= 1'b1;
      else if (nCS_s1_begins_xfer)
          nCS_s1_reg_firsttransfer <= nCS_s1_unreg_firsttransfer;
    end


  //nCS_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign nCS_s1_beginbursttransfer_internal = nCS_s1_begins_xfer;

  //~nCS_s1_write_n assignment, which is an e_mux
  assign nCS_s1_write_n = ~(cpu_data_master_granted_nCS_s1 & cpu_data_master_write);

  assign shifted_address_to_nCS_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //nCS_s1_address mux, which is an e_mux
  assign nCS_s1_address = shifted_address_to_nCS_s1_from_cpu_data_master >> 2;

  //d1_nCS_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_nCS_s1_end_xfer <= 1;
      else if (1)
          d1_nCS_s1_end_xfer <= nCS_s1_end_xfer;
    end


  //nCS_s1_waits_for_read in a cycle, which is an e_mux
  assign nCS_s1_waits_for_read = nCS_s1_in_a_read_cycle & nCS_s1_begins_xfer;

  //nCS_s1_in_a_read_cycle assignment, which is an e_assign
  assign nCS_s1_in_a_read_cycle = cpu_data_master_granted_nCS_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = nCS_s1_in_a_read_cycle;

  //nCS_s1_waits_for_write in a cycle, which is an e_mux
  assign nCS_s1_waits_for_write = nCS_s1_in_a_write_cycle & 0;

  //nCS_s1_in_a_write_cycle assignment, which is an e_assign
  assign nCS_s1_in_a_write_cycle = cpu_data_master_granted_nCS_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = nCS_s1_in_a_write_cycle;

  assign wait_for_nCS_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //nCS/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module nRD_s1_arbitrator (
                           // inputs:
                            clk,
                            cpu_data_master_address_to_slave,
                            cpu_data_master_read,
                            cpu_data_master_waitrequest,
                            cpu_data_master_write,
                            cpu_data_master_writedata,
                            reset_n,

                           // outputs:
                            cpu_data_master_granted_nRD_s1,
                            cpu_data_master_qualified_request_nRD_s1,
                            cpu_data_master_read_data_valid_nRD_s1,
                            cpu_data_master_requests_nRD_s1,
                            d1_nRD_s1_end_xfer,
                            nRD_s1_address,
                            nRD_s1_chipselect,
                            nRD_s1_reset_n,
                            nRD_s1_write_n,
                            nRD_s1_writedata
                         )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output           cpu_data_master_granted_nRD_s1;
  output           cpu_data_master_qualified_request_nRD_s1;
  output           cpu_data_master_read_data_valid_nRD_s1;
  output           cpu_data_master_requests_nRD_s1;
  output           d1_nRD_s1_end_xfer;
  output  [  1: 0] nRD_s1_address;
  output           nRD_s1_chipselect;
  output           nRD_s1_reset_n;
  output           nRD_s1_write_n;
  output           nRD_s1_writedata;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_nRD_s1;
  wire             cpu_data_master_qualified_request_nRD_s1;
  wire             cpu_data_master_read_data_valid_nRD_s1;
  wire             cpu_data_master_requests_nRD_s1;
  wire             cpu_data_master_saved_grant_nRD_s1;
  reg              d1_nRD_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_nRD_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] nRD_s1_address;
  wire             nRD_s1_allgrants;
  wire             nRD_s1_allow_new_arb_cycle;
  wire             nRD_s1_any_bursting_master_saved_grant;
  wire             nRD_s1_any_continuerequest;
  wire             nRD_s1_arb_counter_enable;
  reg     [  2: 0] nRD_s1_arb_share_counter;
  wire    [  2: 0] nRD_s1_arb_share_counter_next_value;
  wire    [  2: 0] nRD_s1_arb_share_set_values;
  wire             nRD_s1_beginbursttransfer_internal;
  wire             nRD_s1_begins_xfer;
  wire             nRD_s1_chipselect;
  wire             nRD_s1_end_xfer;
  wire             nRD_s1_firsttransfer;
  wire             nRD_s1_grant_vector;
  wire             nRD_s1_in_a_read_cycle;
  wire             nRD_s1_in_a_write_cycle;
  wire             nRD_s1_master_qreq_vector;
  wire             nRD_s1_non_bursting_master_requests;
  reg              nRD_s1_reg_firsttransfer;
  wire             nRD_s1_reset_n;
  reg              nRD_s1_slavearbiterlockenable;
  wire             nRD_s1_slavearbiterlockenable2;
  wire             nRD_s1_unreg_firsttransfer;
  wire             nRD_s1_waits_for_read;
  wire             nRD_s1_waits_for_write;
  wire             nRD_s1_write_n;
  wire             nRD_s1_writedata;
  wire    [ 23: 0] shifted_address_to_nRD_s1_from_cpu_data_master;
  wire             wait_for_nRD_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~nRD_s1_end_xfer;
    end


  assign nRD_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_nRD_s1));
  assign cpu_data_master_requests_nRD_s1 = (({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'h81030) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //nRD_s1_arb_share_counter set values, which is an e_mux
  assign nRD_s1_arb_share_set_values = 1;

  //nRD_s1_non_bursting_master_requests mux, which is an e_mux
  assign nRD_s1_non_bursting_master_requests = cpu_data_master_requests_nRD_s1;

  //nRD_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign nRD_s1_any_bursting_master_saved_grant = 0;

  //nRD_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign nRD_s1_arb_share_counter_next_value = nRD_s1_firsttransfer ? (nRD_s1_arb_share_set_values - 1) : |nRD_s1_arb_share_counter ? (nRD_s1_arb_share_counter - 1) : 0;

  //nRD_s1_allgrants all slave grants, which is an e_mux
  assign nRD_s1_allgrants = |nRD_s1_grant_vector;

  //nRD_s1_end_xfer assignment, which is an e_assign
  assign nRD_s1_end_xfer = ~(nRD_s1_waits_for_read | nRD_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_nRD_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_nRD_s1 = nRD_s1_end_xfer & (~nRD_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //nRD_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign nRD_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_nRD_s1 & nRD_s1_allgrants) | (end_xfer_arb_share_counter_term_nRD_s1 & ~nRD_s1_non_bursting_master_requests);

  //nRD_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nRD_s1_arb_share_counter <= 0;
      else if (nRD_s1_arb_counter_enable)
          nRD_s1_arb_share_counter <= nRD_s1_arb_share_counter_next_value;
    end


  //nRD_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nRD_s1_slavearbiterlockenable <= 0;
      else if ((|nRD_s1_master_qreq_vector & end_xfer_arb_share_counter_term_nRD_s1) | (end_xfer_arb_share_counter_term_nRD_s1 & ~nRD_s1_non_bursting_master_requests))
          nRD_s1_slavearbiterlockenable <= |nRD_s1_arb_share_counter_next_value;
    end


  //cpu/data_master nRD/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = nRD_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //nRD_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign nRD_s1_slavearbiterlockenable2 = |nRD_s1_arb_share_counter_next_value;

  //cpu/data_master nRD/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = nRD_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //nRD_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign nRD_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_nRD_s1 = cpu_data_master_requests_nRD_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //nRD_s1_writedata mux, which is an e_mux
  assign nRD_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_nRD_s1 = cpu_data_master_qualified_request_nRD_s1;

  //cpu/data_master saved-grant nRD/s1, which is an e_assign
  assign cpu_data_master_saved_grant_nRD_s1 = cpu_data_master_requests_nRD_s1;

  //allow new arb cycle for nRD/s1, which is an e_assign
  assign nRD_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign nRD_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign nRD_s1_master_qreq_vector = 1;

  //nRD_s1_reset_n assignment, which is an e_assign
  assign nRD_s1_reset_n = reset_n;

  assign nRD_s1_chipselect = cpu_data_master_granted_nRD_s1;
  //nRD_s1_firsttransfer first transaction, which is an e_assign
  assign nRD_s1_firsttransfer = nRD_s1_begins_xfer ? nRD_s1_unreg_firsttransfer : nRD_s1_reg_firsttransfer;

  //nRD_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign nRD_s1_unreg_firsttransfer = ~(nRD_s1_slavearbiterlockenable & nRD_s1_any_continuerequest);

  //nRD_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nRD_s1_reg_firsttransfer <= 1'b1;
      else if (nRD_s1_begins_xfer)
          nRD_s1_reg_firsttransfer <= nRD_s1_unreg_firsttransfer;
    end


  //nRD_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign nRD_s1_beginbursttransfer_internal = nRD_s1_begins_xfer;

  //~nRD_s1_write_n assignment, which is an e_mux
  assign nRD_s1_write_n = ~(cpu_data_master_granted_nRD_s1 & cpu_data_master_write);

  assign shifted_address_to_nRD_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //nRD_s1_address mux, which is an e_mux
  assign nRD_s1_address = shifted_address_to_nRD_s1_from_cpu_data_master >> 2;

  //d1_nRD_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_nRD_s1_end_xfer <= 1;
      else if (1)
          d1_nRD_s1_end_xfer <= nRD_s1_end_xfer;
    end


  //nRD_s1_waits_for_read in a cycle, which is an e_mux
  assign nRD_s1_waits_for_read = nRD_s1_in_a_read_cycle & nRD_s1_begins_xfer;

  //nRD_s1_in_a_read_cycle assignment, which is an e_assign
  assign nRD_s1_in_a_read_cycle = cpu_data_master_granted_nRD_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = nRD_s1_in_a_read_cycle;

  //nRD_s1_waits_for_write in a cycle, which is an e_mux
  assign nRD_s1_waits_for_write = nRD_s1_in_a_write_cycle & 0;

  //nRD_s1_in_a_write_cycle assignment, which is an e_assign
  assign nRD_s1_in_a_write_cycle = cpu_data_master_granted_nRD_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = nRD_s1_in_a_write_cycle;

  assign wait_for_nRD_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //nRD/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module nWR_s1_arbitrator (
                           // inputs:
                            clk,
                            cpu_data_master_address_to_slave,
                            cpu_data_master_read,
                            cpu_data_master_waitrequest,
                            cpu_data_master_write,
                            cpu_data_master_writedata,
                            reset_n,

                           // outputs:
                            cpu_data_master_granted_nWR_s1,
                            cpu_data_master_qualified_request_nWR_s1,
                            cpu_data_master_read_data_valid_nWR_s1,
                            cpu_data_master_requests_nWR_s1,
                            d1_nWR_s1_end_xfer,
                            nWR_s1_address,
                            nWR_s1_chipselect,
                            nWR_s1_reset_n,
                            nWR_s1_write_n,
                            nWR_s1_writedata
                         )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output           cpu_data_master_granted_nWR_s1;
  output           cpu_data_master_qualified_request_nWR_s1;
  output           cpu_data_master_read_data_valid_nWR_s1;
  output           cpu_data_master_requests_nWR_s1;
  output           d1_nWR_s1_end_xfer;
  output  [  1: 0] nWR_s1_address;
  output           nWR_s1_chipselect;
  output           nWR_s1_reset_n;
  output           nWR_s1_write_n;
  output           nWR_s1_writedata;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_nWR_s1;
  wire             cpu_data_master_qualified_request_nWR_s1;
  wire             cpu_data_master_read_data_valid_nWR_s1;
  wire             cpu_data_master_requests_nWR_s1;
  wire             cpu_data_master_saved_grant_nWR_s1;
  reg              d1_nWR_s1_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_nWR_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [  1: 0] nWR_s1_address;
  wire             nWR_s1_allgrants;
  wire             nWR_s1_allow_new_arb_cycle;
  wire             nWR_s1_any_bursting_master_saved_grant;
  wire             nWR_s1_any_continuerequest;
  wire             nWR_s1_arb_counter_enable;
  reg     [  2: 0] nWR_s1_arb_share_counter;
  wire    [  2: 0] nWR_s1_arb_share_counter_next_value;
  wire    [  2: 0] nWR_s1_arb_share_set_values;
  wire             nWR_s1_beginbursttransfer_internal;
  wire             nWR_s1_begins_xfer;
  wire             nWR_s1_chipselect;
  wire             nWR_s1_end_xfer;
  wire             nWR_s1_firsttransfer;
  wire             nWR_s1_grant_vector;
  wire             nWR_s1_in_a_read_cycle;
  wire             nWR_s1_in_a_write_cycle;
  wire             nWR_s1_master_qreq_vector;
  wire             nWR_s1_non_bursting_master_requests;
  reg              nWR_s1_reg_firsttransfer;
  wire             nWR_s1_reset_n;
  reg              nWR_s1_slavearbiterlockenable;
  wire             nWR_s1_slavearbiterlockenable2;
  wire             nWR_s1_unreg_firsttransfer;
  wire             nWR_s1_waits_for_read;
  wire             nWR_s1_waits_for_write;
  wire             nWR_s1_write_n;
  wire             nWR_s1_writedata;
  wire    [ 23: 0] shifted_address_to_nWR_s1_from_cpu_data_master;
  wire             wait_for_nWR_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~nWR_s1_end_xfer;
    end


  assign nWR_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_nWR_s1));
  assign cpu_data_master_requests_nWR_s1 = (({cpu_data_master_address_to_slave[23 : 4] , 4'b0} == 24'h81050) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_write;
  //nWR_s1_arb_share_counter set values, which is an e_mux
  assign nWR_s1_arb_share_set_values = 1;

  //nWR_s1_non_bursting_master_requests mux, which is an e_mux
  assign nWR_s1_non_bursting_master_requests = cpu_data_master_requests_nWR_s1;

  //nWR_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign nWR_s1_any_bursting_master_saved_grant = 0;

  //nWR_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign nWR_s1_arb_share_counter_next_value = nWR_s1_firsttransfer ? (nWR_s1_arb_share_set_values - 1) : |nWR_s1_arb_share_counter ? (nWR_s1_arb_share_counter - 1) : 0;

  //nWR_s1_allgrants all slave grants, which is an e_mux
  assign nWR_s1_allgrants = |nWR_s1_grant_vector;

  //nWR_s1_end_xfer assignment, which is an e_assign
  assign nWR_s1_end_xfer = ~(nWR_s1_waits_for_read | nWR_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_nWR_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_nWR_s1 = nWR_s1_end_xfer & (~nWR_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //nWR_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign nWR_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_nWR_s1 & nWR_s1_allgrants) | (end_xfer_arb_share_counter_term_nWR_s1 & ~nWR_s1_non_bursting_master_requests);

  //nWR_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nWR_s1_arb_share_counter <= 0;
      else if (nWR_s1_arb_counter_enable)
          nWR_s1_arb_share_counter <= nWR_s1_arb_share_counter_next_value;
    end


  //nWR_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nWR_s1_slavearbiterlockenable <= 0;
      else if ((|nWR_s1_master_qreq_vector & end_xfer_arb_share_counter_term_nWR_s1) | (end_xfer_arb_share_counter_term_nWR_s1 & ~nWR_s1_non_bursting_master_requests))
          nWR_s1_slavearbiterlockenable <= |nWR_s1_arb_share_counter_next_value;
    end


  //cpu/data_master nWR/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = nWR_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //nWR_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign nWR_s1_slavearbiterlockenable2 = |nWR_s1_arb_share_counter_next_value;

  //cpu/data_master nWR/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = nWR_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //nWR_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign nWR_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_nWR_s1 = cpu_data_master_requests_nWR_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //nWR_s1_writedata mux, which is an e_mux
  assign nWR_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_nWR_s1 = cpu_data_master_qualified_request_nWR_s1;

  //cpu/data_master saved-grant nWR/s1, which is an e_assign
  assign cpu_data_master_saved_grant_nWR_s1 = cpu_data_master_requests_nWR_s1;

  //allow new arb cycle for nWR/s1, which is an e_assign
  assign nWR_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign nWR_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign nWR_s1_master_qreq_vector = 1;

  //nWR_s1_reset_n assignment, which is an e_assign
  assign nWR_s1_reset_n = reset_n;

  assign nWR_s1_chipselect = cpu_data_master_granted_nWR_s1;
  //nWR_s1_firsttransfer first transaction, which is an e_assign
  assign nWR_s1_firsttransfer = nWR_s1_begins_xfer ? nWR_s1_unreg_firsttransfer : nWR_s1_reg_firsttransfer;

  //nWR_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign nWR_s1_unreg_firsttransfer = ~(nWR_s1_slavearbiterlockenable & nWR_s1_any_continuerequest);

  //nWR_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          nWR_s1_reg_firsttransfer <= 1'b1;
      else if (nWR_s1_begins_xfer)
          nWR_s1_reg_firsttransfer <= nWR_s1_unreg_firsttransfer;
    end


  //nWR_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign nWR_s1_beginbursttransfer_internal = nWR_s1_begins_xfer;

  //~nWR_s1_write_n assignment, which is an e_mux
  assign nWR_s1_write_n = ~(cpu_data_master_granted_nWR_s1 & cpu_data_master_write);

  assign shifted_address_to_nWR_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //nWR_s1_address mux, which is an e_mux
  assign nWR_s1_address = shifted_address_to_nWR_s1_from_cpu_data_master >> 2;

  //d1_nWR_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_nWR_s1_end_xfer <= 1;
      else if (1)
          d1_nWR_s1_end_xfer <= nWR_s1_end_xfer;
    end


  //nWR_s1_waits_for_read in a cycle, which is an e_mux
  assign nWR_s1_waits_for_read = nWR_s1_in_a_read_cycle & nWR_s1_begins_xfer;

  //nWR_s1_in_a_read_cycle assignment, which is an e_assign
  assign nWR_s1_in_a_read_cycle = cpu_data_master_granted_nWR_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = nWR_s1_in_a_read_cycle;

  //nWR_s1_waits_for_write in a cycle, which is an e_mux
  assign nWR_s1_waits_for_write = nWR_s1_in_a_write_cycle & 0;

  //nWR_s1_in_a_write_cycle assignment, which is an e_assign
  assign nWR_s1_in_a_write_cycle = cpu_data_master_granted_nWR_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = nWR_s1_in_a_write_cycle;

  assign wait_for_nWR_s1_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //nWR/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module ps2_0_avalon_PS2_slave_arbitrator (
                                           // inputs:
                                            clk,
                                            cpu_data_master_address_to_slave,
                                            cpu_data_master_byteenable,
                                            cpu_data_master_read,
                                            cpu_data_master_waitrequest,
                                            cpu_data_master_write,
                                            cpu_data_master_writedata,
                                            ps2_0_avalon_PS2_slave_irq,
                                            ps2_0_avalon_PS2_slave_readdata,
                                            ps2_0_avalon_PS2_slave_waitrequest,
                                            reset_n,

                                           // outputs:
                                            cpu_data_master_granted_ps2_0_avalon_PS2_slave,
                                            cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave,
                                            cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave,
                                            cpu_data_master_requests_ps2_0_avalon_PS2_slave,
                                            d1_ps2_0_avalon_PS2_slave_end_xfer,
                                            ps2_0_avalon_PS2_slave_address,
                                            ps2_0_avalon_PS2_slave_byteenable,
                                            ps2_0_avalon_PS2_slave_chipselect,
                                            ps2_0_avalon_PS2_slave_irq_from_sa,
                                            ps2_0_avalon_PS2_slave_read,
                                            ps2_0_avalon_PS2_slave_readdata_from_sa,
                                            ps2_0_avalon_PS2_slave_waitrequest_from_sa,
                                            ps2_0_avalon_PS2_slave_write,
                                            ps2_0_avalon_PS2_slave_writedata,
                                            registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave
                                         )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output           cpu_data_master_granted_ps2_0_avalon_PS2_slave;
  output           cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave;
  output           cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave;
  output           cpu_data_master_requests_ps2_0_avalon_PS2_slave;
  output           d1_ps2_0_avalon_PS2_slave_end_xfer;
  output           ps2_0_avalon_PS2_slave_address;
  output  [  3: 0] ps2_0_avalon_PS2_slave_byteenable;
  output           ps2_0_avalon_PS2_slave_chipselect;
  output           ps2_0_avalon_PS2_slave_irq_from_sa;
  output           ps2_0_avalon_PS2_slave_read;
  output  [ 31: 0] ps2_0_avalon_PS2_slave_readdata_from_sa;
  output           ps2_0_avalon_PS2_slave_waitrequest_from_sa;
  output           ps2_0_avalon_PS2_slave_write;
  output  [ 31: 0] ps2_0_avalon_PS2_slave_writedata;
  output           registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            ps2_0_avalon_PS2_slave_irq;
  input   [ 31: 0] ps2_0_avalon_PS2_slave_readdata;
  input            ps2_0_avalon_PS2_slave_waitrequest;
  input            reset_n;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_ps2_0_avalon_PS2_slave;
  wire             cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave;
  wire             cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave;
  reg              cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register;
  wire             cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register_in;
  wire             cpu_data_master_requests_ps2_0_avalon_PS2_slave;
  wire             cpu_data_master_saved_grant_ps2_0_avalon_PS2_slave;
  reg              d1_ps2_0_avalon_PS2_slave_end_xfer;
  reg              d1_reasons_to_wait;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_ps2_0_avalon_PS2_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire             p1_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register;
  wire             ps2_0_avalon_PS2_slave_address;
  wire             ps2_0_avalon_PS2_slave_allgrants;
  wire             ps2_0_avalon_PS2_slave_allow_new_arb_cycle;
  wire             ps2_0_avalon_PS2_slave_any_bursting_master_saved_grant;
  wire             ps2_0_avalon_PS2_slave_any_continuerequest;
  wire             ps2_0_avalon_PS2_slave_arb_counter_enable;
  reg     [  2: 0] ps2_0_avalon_PS2_slave_arb_share_counter;
  wire    [  2: 0] ps2_0_avalon_PS2_slave_arb_share_counter_next_value;
  wire    [  2: 0] ps2_0_avalon_PS2_slave_arb_share_set_values;
  wire             ps2_0_avalon_PS2_slave_beginbursttransfer_internal;
  wire             ps2_0_avalon_PS2_slave_begins_xfer;
  wire    [  3: 0] ps2_0_avalon_PS2_slave_byteenable;
  wire             ps2_0_avalon_PS2_slave_chipselect;
  wire             ps2_0_avalon_PS2_slave_end_xfer;
  wire             ps2_0_avalon_PS2_slave_firsttransfer;
  wire             ps2_0_avalon_PS2_slave_grant_vector;
  wire             ps2_0_avalon_PS2_slave_in_a_read_cycle;
  wire             ps2_0_avalon_PS2_slave_in_a_write_cycle;
  wire             ps2_0_avalon_PS2_slave_irq_from_sa;
  wire             ps2_0_avalon_PS2_slave_master_qreq_vector;
  wire             ps2_0_avalon_PS2_slave_non_bursting_master_requests;
  wire             ps2_0_avalon_PS2_slave_read;
  wire    [ 31: 0] ps2_0_avalon_PS2_slave_readdata_from_sa;
  reg              ps2_0_avalon_PS2_slave_reg_firsttransfer;
  reg              ps2_0_avalon_PS2_slave_slavearbiterlockenable;
  wire             ps2_0_avalon_PS2_slave_slavearbiterlockenable2;
  wire             ps2_0_avalon_PS2_slave_unreg_firsttransfer;
  wire             ps2_0_avalon_PS2_slave_waitrequest_from_sa;
  wire             ps2_0_avalon_PS2_slave_waits_for_read;
  wire             ps2_0_avalon_PS2_slave_waits_for_write;
  wire             ps2_0_avalon_PS2_slave_write;
  wire    [ 31: 0] ps2_0_avalon_PS2_slave_writedata;
  wire             registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave;
  wire    [ 23: 0] shifted_address_to_ps2_0_avalon_PS2_slave_from_cpu_data_master;
  wire             wait_for_ps2_0_avalon_PS2_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~ps2_0_avalon_PS2_slave_end_xfer;
    end


  assign ps2_0_avalon_PS2_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave));
  //assign ps2_0_avalon_PS2_slave_readdata_from_sa = ps2_0_avalon_PS2_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign ps2_0_avalon_PS2_slave_readdata_from_sa = ps2_0_avalon_PS2_slave_readdata;

  assign cpu_data_master_requests_ps2_0_avalon_PS2_slave = ({cpu_data_master_address_to_slave[23 : 3] , 3'b0} == 24'h810b0) & (cpu_data_master_read | cpu_data_master_write);
  //assign ps2_0_avalon_PS2_slave_waitrequest_from_sa = ps2_0_avalon_PS2_slave_waitrequest so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign ps2_0_avalon_PS2_slave_waitrequest_from_sa = ps2_0_avalon_PS2_slave_waitrequest;

  //registered rdv signal_name registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave assignment, which is an e_assign
  assign registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave = cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register_in;

  //ps2_0_avalon_PS2_slave_arb_share_counter set values, which is an e_mux
  assign ps2_0_avalon_PS2_slave_arb_share_set_values = 1;

  //ps2_0_avalon_PS2_slave_non_bursting_master_requests mux, which is an e_mux
  assign ps2_0_avalon_PS2_slave_non_bursting_master_requests = cpu_data_master_requests_ps2_0_avalon_PS2_slave;

  //ps2_0_avalon_PS2_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign ps2_0_avalon_PS2_slave_any_bursting_master_saved_grant = 0;

  //ps2_0_avalon_PS2_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign ps2_0_avalon_PS2_slave_arb_share_counter_next_value = ps2_0_avalon_PS2_slave_firsttransfer ? (ps2_0_avalon_PS2_slave_arb_share_set_values - 1) : |ps2_0_avalon_PS2_slave_arb_share_counter ? (ps2_0_avalon_PS2_slave_arb_share_counter - 1) : 0;

  //ps2_0_avalon_PS2_slave_allgrants all slave grants, which is an e_mux
  assign ps2_0_avalon_PS2_slave_allgrants = |ps2_0_avalon_PS2_slave_grant_vector;

  //ps2_0_avalon_PS2_slave_end_xfer assignment, which is an e_assign
  assign ps2_0_avalon_PS2_slave_end_xfer = ~(ps2_0_avalon_PS2_slave_waits_for_read | ps2_0_avalon_PS2_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_ps2_0_avalon_PS2_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_ps2_0_avalon_PS2_slave = ps2_0_avalon_PS2_slave_end_xfer & (~ps2_0_avalon_PS2_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //ps2_0_avalon_PS2_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign ps2_0_avalon_PS2_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_ps2_0_avalon_PS2_slave & ps2_0_avalon_PS2_slave_allgrants) | (end_xfer_arb_share_counter_term_ps2_0_avalon_PS2_slave & ~ps2_0_avalon_PS2_slave_non_bursting_master_requests);

  //ps2_0_avalon_PS2_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          ps2_0_avalon_PS2_slave_arb_share_counter <= 0;
      else if (ps2_0_avalon_PS2_slave_arb_counter_enable)
          ps2_0_avalon_PS2_slave_arb_share_counter <= ps2_0_avalon_PS2_slave_arb_share_counter_next_value;
    end


  //ps2_0_avalon_PS2_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          ps2_0_avalon_PS2_slave_slavearbiterlockenable <= 0;
      else if ((|ps2_0_avalon_PS2_slave_master_qreq_vector & end_xfer_arb_share_counter_term_ps2_0_avalon_PS2_slave) | (end_xfer_arb_share_counter_term_ps2_0_avalon_PS2_slave & ~ps2_0_avalon_PS2_slave_non_bursting_master_requests))
          ps2_0_avalon_PS2_slave_slavearbiterlockenable <= |ps2_0_avalon_PS2_slave_arb_share_counter_next_value;
    end


  //cpu/data_master ps2_0/avalon_PS2_slave arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = ps2_0_avalon_PS2_slave_slavearbiterlockenable & cpu_data_master_continuerequest;

  //ps2_0_avalon_PS2_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign ps2_0_avalon_PS2_slave_slavearbiterlockenable2 = |ps2_0_avalon_PS2_slave_arb_share_counter_next_value;

  //cpu/data_master ps2_0/avalon_PS2_slave arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = ps2_0_avalon_PS2_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //ps2_0_avalon_PS2_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign ps2_0_avalon_PS2_slave_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave = cpu_data_master_requests_ps2_0_avalon_PS2_slave & ~((cpu_data_master_read & ((|cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register))) | ((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register_in = cpu_data_master_granted_ps2_0_avalon_PS2_slave & cpu_data_master_read & ~ps2_0_avalon_PS2_slave_waits_for_read & ~(|cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register);

  //shift register p1 cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register = {cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register, cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register_in};

  //cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register <= 0;
      else if (1)
          cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register <= p1_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register;
    end


  //local readdatavalid cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave, which is an e_mux
  assign cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave = cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave_shift_register;

  //ps2_0_avalon_PS2_slave_writedata mux, which is an e_mux
  assign ps2_0_avalon_PS2_slave_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_ps2_0_avalon_PS2_slave = cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave;

  //cpu/data_master saved-grant ps2_0/avalon_PS2_slave, which is an e_assign
  assign cpu_data_master_saved_grant_ps2_0_avalon_PS2_slave = cpu_data_master_requests_ps2_0_avalon_PS2_slave;

  //allow new arb cycle for ps2_0/avalon_PS2_slave, which is an e_assign
  assign ps2_0_avalon_PS2_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign ps2_0_avalon_PS2_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign ps2_0_avalon_PS2_slave_master_qreq_vector = 1;

  assign ps2_0_avalon_PS2_slave_chipselect = cpu_data_master_granted_ps2_0_avalon_PS2_slave;
  //ps2_0_avalon_PS2_slave_firsttransfer first transaction, which is an e_assign
  assign ps2_0_avalon_PS2_slave_firsttransfer = ps2_0_avalon_PS2_slave_begins_xfer ? ps2_0_avalon_PS2_slave_unreg_firsttransfer : ps2_0_avalon_PS2_slave_reg_firsttransfer;

  //ps2_0_avalon_PS2_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign ps2_0_avalon_PS2_slave_unreg_firsttransfer = ~(ps2_0_avalon_PS2_slave_slavearbiterlockenable & ps2_0_avalon_PS2_slave_any_continuerequest);

  //ps2_0_avalon_PS2_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          ps2_0_avalon_PS2_slave_reg_firsttransfer <= 1'b1;
      else if (ps2_0_avalon_PS2_slave_begins_xfer)
          ps2_0_avalon_PS2_slave_reg_firsttransfer <= ps2_0_avalon_PS2_slave_unreg_firsttransfer;
    end


  //ps2_0_avalon_PS2_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign ps2_0_avalon_PS2_slave_beginbursttransfer_internal = ps2_0_avalon_PS2_slave_begins_xfer;

  //ps2_0_avalon_PS2_slave_read assignment, which is an e_mux
  assign ps2_0_avalon_PS2_slave_read = cpu_data_master_granted_ps2_0_avalon_PS2_slave & cpu_data_master_read;

  //ps2_0_avalon_PS2_slave_write assignment, which is an e_mux
  assign ps2_0_avalon_PS2_slave_write = cpu_data_master_granted_ps2_0_avalon_PS2_slave & cpu_data_master_write;

  assign shifted_address_to_ps2_0_avalon_PS2_slave_from_cpu_data_master = cpu_data_master_address_to_slave;
  //ps2_0_avalon_PS2_slave_address mux, which is an e_mux
  assign ps2_0_avalon_PS2_slave_address = shifted_address_to_ps2_0_avalon_PS2_slave_from_cpu_data_master >> 2;

  //d1_ps2_0_avalon_PS2_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_ps2_0_avalon_PS2_slave_end_xfer <= 1;
      else if (1)
          d1_ps2_0_avalon_PS2_slave_end_xfer <= ps2_0_avalon_PS2_slave_end_xfer;
    end


  //ps2_0_avalon_PS2_slave_waits_for_read in a cycle, which is an e_mux
  assign ps2_0_avalon_PS2_slave_waits_for_read = ps2_0_avalon_PS2_slave_in_a_read_cycle & ps2_0_avalon_PS2_slave_waitrequest_from_sa;

  //ps2_0_avalon_PS2_slave_in_a_read_cycle assignment, which is an e_assign
  assign ps2_0_avalon_PS2_slave_in_a_read_cycle = cpu_data_master_granted_ps2_0_avalon_PS2_slave & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = ps2_0_avalon_PS2_slave_in_a_read_cycle;

  //ps2_0_avalon_PS2_slave_waits_for_write in a cycle, which is an e_mux
  assign ps2_0_avalon_PS2_slave_waits_for_write = ps2_0_avalon_PS2_slave_in_a_write_cycle & ps2_0_avalon_PS2_slave_waitrequest_from_sa;

  //ps2_0_avalon_PS2_slave_in_a_write_cycle assignment, which is an e_assign
  assign ps2_0_avalon_PS2_slave_in_a_write_cycle = cpu_data_master_granted_ps2_0_avalon_PS2_slave & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = ps2_0_avalon_PS2_slave_in_a_write_cycle;

  assign wait_for_ps2_0_avalon_PS2_slave_counter = 0;
  //ps2_0_avalon_PS2_slave_byteenable byte enable port mux, which is an e_mux
  assign ps2_0_avalon_PS2_slave_byteenable = (cpu_data_master_granted_ps2_0_avalon_PS2_slave)? cpu_data_master_byteenable :
    -1;

  //assign ps2_0_avalon_PS2_slave_irq_from_sa = ps2_0_avalon_PS2_slave_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign ps2_0_avalon_PS2_slave_irq_from_sa = ps2_0_avalon_PS2_slave_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //ps2_0/avalon_PS2_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module sram_0_avalon_sram_slave_arbitrator (
                                             // inputs:
                                              clk,
                                              cpu_data_master_address_to_slave,
                                              cpu_data_master_byteenable,
                                              cpu_data_master_dbs_address,
                                              cpu_data_master_dbs_write_16,
                                              cpu_data_master_no_byte_enables_and_last_term,
                                              cpu_data_master_read,
                                              cpu_data_master_waitrequest,
                                              cpu_data_master_write,
                                              cpu_instruction_master_address_to_slave,
                                              cpu_instruction_master_dbs_address,
                                              cpu_instruction_master_latency_counter,
                                              cpu_instruction_master_read,
                                              reset_n,
                                              sram_0_avalon_sram_slave_readdata,

                                             // outputs:
                                              cpu_data_master_byteenable_sram_0_avalon_sram_slave,
                                              cpu_data_master_granted_sram_0_avalon_sram_slave,
                                              cpu_data_master_qualified_request_sram_0_avalon_sram_slave,
                                              cpu_data_master_read_data_valid_sram_0_avalon_sram_slave,
                                              cpu_data_master_requests_sram_0_avalon_sram_slave,
                                              cpu_instruction_master_granted_sram_0_avalon_sram_slave,
                                              cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave,
                                              cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave,
                                              cpu_instruction_master_requests_sram_0_avalon_sram_slave,
                                              d1_sram_0_avalon_sram_slave_end_xfer,
                                              registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave,
                                              sram_0_avalon_sram_slave_address,
                                              sram_0_avalon_sram_slave_byteenable,
                                              sram_0_avalon_sram_slave_chipselect,
                                              sram_0_avalon_sram_slave_read,
                                              sram_0_avalon_sram_slave_readdata_from_sa,
                                              sram_0_avalon_sram_slave_write,
                                              sram_0_avalon_sram_slave_writedata
                                           )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [  1: 0] cpu_data_master_byteenable_sram_0_avalon_sram_slave;
  output           cpu_data_master_granted_sram_0_avalon_sram_slave;
  output           cpu_data_master_qualified_request_sram_0_avalon_sram_slave;
  output           cpu_data_master_read_data_valid_sram_0_avalon_sram_slave;
  output           cpu_data_master_requests_sram_0_avalon_sram_slave;
  output           cpu_instruction_master_granted_sram_0_avalon_sram_slave;
  output           cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave;
  output           cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave;
  output           cpu_instruction_master_requests_sram_0_avalon_sram_slave;
  output           d1_sram_0_avalon_sram_slave_end_xfer;
  output           registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave;
  output  [ 17: 0] sram_0_avalon_sram_slave_address;
  output  [  1: 0] sram_0_avalon_sram_slave_byteenable;
  output           sram_0_avalon_sram_slave_chipselect;
  output           sram_0_avalon_sram_slave_read;
  output  [ 15: 0] sram_0_avalon_sram_slave_readdata_from_sa;
  output           sram_0_avalon_sram_slave_write;
  output  [ 15: 0] sram_0_avalon_sram_slave_writedata;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input   [  1: 0] cpu_data_master_dbs_address;
  input   [ 15: 0] cpu_data_master_dbs_write_16;
  input            cpu_data_master_no_byte_enables_and_last_term;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 23: 0] cpu_instruction_master_address_to_slave;
  input   [  1: 0] cpu_instruction_master_dbs_address;
  input   [  1: 0] cpu_instruction_master_latency_counter;
  input            cpu_instruction_master_read;
  input            reset_n;
  input   [ 15: 0] sram_0_avalon_sram_slave_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire    [  1: 0] cpu_data_master_byteenable_sram_0_avalon_sram_slave;
  wire    [  1: 0] cpu_data_master_byteenable_sram_0_avalon_sram_slave_segment_0;
  wire    [  1: 0] cpu_data_master_byteenable_sram_0_avalon_sram_slave_segment_1;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_sram_0_avalon_sram_slave;
  wire             cpu_data_master_qualified_request_sram_0_avalon_sram_slave;
  wire             cpu_data_master_read_data_valid_sram_0_avalon_sram_slave;
  reg     [  1: 0] cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register;
  wire             cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register_in;
  wire             cpu_data_master_requests_sram_0_avalon_sram_slave;
  wire             cpu_data_master_saved_grant_sram_0_avalon_sram_slave;
  wire             cpu_instruction_master_arbiterlock;
  wire             cpu_instruction_master_arbiterlock2;
  wire             cpu_instruction_master_continuerequest;
  wire             cpu_instruction_master_granted_sram_0_avalon_sram_slave;
  wire             cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave;
  wire             cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave;
  reg     [  1: 0] cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register;
  wire             cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register_in;
  wire             cpu_instruction_master_requests_sram_0_avalon_sram_slave;
  wire             cpu_instruction_master_saved_grant_sram_0_avalon_sram_slave;
  reg              d1_reasons_to_wait;
  reg              d1_sram_0_avalon_sram_slave_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_sram_0_avalon_sram_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg              last_cycle_cpu_data_master_granted_slave_sram_0_avalon_sram_slave;
  reg              last_cycle_cpu_instruction_master_granted_slave_sram_0_avalon_sram_slave;
  wire    [  1: 0] p1_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register;
  wire    [  1: 0] p1_cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register;
  wire             registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave;
  wire    [ 23: 0] shifted_address_to_sram_0_avalon_sram_slave_from_cpu_data_master;
  wire    [ 23: 0] shifted_address_to_sram_0_avalon_sram_slave_from_cpu_instruction_master;
  wire    [ 17: 0] sram_0_avalon_sram_slave_address;
  wire             sram_0_avalon_sram_slave_allgrants;
  wire             sram_0_avalon_sram_slave_allow_new_arb_cycle;
  wire             sram_0_avalon_sram_slave_any_bursting_master_saved_grant;
  wire             sram_0_avalon_sram_slave_any_continuerequest;
  reg     [  1: 0] sram_0_avalon_sram_slave_arb_addend;
  wire             sram_0_avalon_sram_slave_arb_counter_enable;
  reg     [  2: 0] sram_0_avalon_sram_slave_arb_share_counter;
  wire    [  2: 0] sram_0_avalon_sram_slave_arb_share_counter_next_value;
  wire    [  2: 0] sram_0_avalon_sram_slave_arb_share_set_values;
  wire    [  1: 0] sram_0_avalon_sram_slave_arb_winner;
  wire             sram_0_avalon_sram_slave_arbitration_holdoff_internal;
  wire             sram_0_avalon_sram_slave_beginbursttransfer_internal;
  wire             sram_0_avalon_sram_slave_begins_xfer;
  wire    [  1: 0] sram_0_avalon_sram_slave_byteenable;
  wire             sram_0_avalon_sram_slave_chipselect;
  wire    [  3: 0] sram_0_avalon_sram_slave_chosen_master_double_vector;
  wire    [  1: 0] sram_0_avalon_sram_slave_chosen_master_rot_left;
  wire             sram_0_avalon_sram_slave_end_xfer;
  wire             sram_0_avalon_sram_slave_firsttransfer;
  wire    [  1: 0] sram_0_avalon_sram_slave_grant_vector;
  wire             sram_0_avalon_sram_slave_in_a_read_cycle;
  wire             sram_0_avalon_sram_slave_in_a_write_cycle;
  wire    [  1: 0] sram_0_avalon_sram_slave_master_qreq_vector;
  wire             sram_0_avalon_sram_slave_non_bursting_master_requests;
  wire             sram_0_avalon_sram_slave_read;
  wire    [ 15: 0] sram_0_avalon_sram_slave_readdata_from_sa;
  reg              sram_0_avalon_sram_slave_reg_firsttransfer;
  reg     [  1: 0] sram_0_avalon_sram_slave_saved_chosen_master_vector;
  reg              sram_0_avalon_sram_slave_slavearbiterlockenable;
  wire             sram_0_avalon_sram_slave_slavearbiterlockenable2;
  wire             sram_0_avalon_sram_slave_unreg_firsttransfer;
  wire             sram_0_avalon_sram_slave_waits_for_read;
  wire             sram_0_avalon_sram_slave_waits_for_write;
  wire             sram_0_avalon_sram_slave_write;
  wire    [ 15: 0] sram_0_avalon_sram_slave_writedata;
  wire             wait_for_sram_0_avalon_sram_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~sram_0_avalon_sram_slave_end_xfer;
    end


  assign sram_0_avalon_sram_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_sram_0_avalon_sram_slave | cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave));
  //assign sram_0_avalon_sram_slave_readdata_from_sa = sram_0_avalon_sram_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sram_0_avalon_sram_slave_readdata_from_sa = sram_0_avalon_sram_slave_readdata;

  assign cpu_data_master_requests_sram_0_avalon_sram_slave = ({cpu_data_master_address_to_slave[23 : 19] , 19'b0} == 24'h0) & (cpu_data_master_read | cpu_data_master_write);
  //registered rdv signal_name registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave assignment, which is an e_assign
  assign registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave = cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register[0];

  //sram_0_avalon_sram_slave_arb_share_counter set values, which is an e_mux
  assign sram_0_avalon_sram_slave_arb_share_set_values = (cpu_data_master_granted_sram_0_avalon_sram_slave)? 2 :
    (cpu_instruction_master_granted_sram_0_avalon_sram_slave)? 2 :
    (cpu_data_master_granted_sram_0_avalon_sram_slave)? 2 :
    (cpu_instruction_master_granted_sram_0_avalon_sram_slave)? 2 :
    1;

  //sram_0_avalon_sram_slave_non_bursting_master_requests mux, which is an e_mux
  assign sram_0_avalon_sram_slave_non_bursting_master_requests = cpu_data_master_requests_sram_0_avalon_sram_slave |
    cpu_instruction_master_requests_sram_0_avalon_sram_slave |
    cpu_data_master_requests_sram_0_avalon_sram_slave |
    cpu_instruction_master_requests_sram_0_avalon_sram_slave;

  //sram_0_avalon_sram_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign sram_0_avalon_sram_slave_any_bursting_master_saved_grant = 0;

  //sram_0_avalon_sram_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign sram_0_avalon_sram_slave_arb_share_counter_next_value = sram_0_avalon_sram_slave_firsttransfer ? (sram_0_avalon_sram_slave_arb_share_set_values - 1) : |sram_0_avalon_sram_slave_arb_share_counter ? (sram_0_avalon_sram_slave_arb_share_counter - 1) : 0;

  //sram_0_avalon_sram_slave_allgrants all slave grants, which is an e_mux
  assign sram_0_avalon_sram_slave_allgrants = |sram_0_avalon_sram_slave_grant_vector |
    |sram_0_avalon_sram_slave_grant_vector |
    |sram_0_avalon_sram_slave_grant_vector |
    |sram_0_avalon_sram_slave_grant_vector;

  //sram_0_avalon_sram_slave_end_xfer assignment, which is an e_assign
  assign sram_0_avalon_sram_slave_end_xfer = ~(sram_0_avalon_sram_slave_waits_for_read | sram_0_avalon_sram_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_sram_0_avalon_sram_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_sram_0_avalon_sram_slave = sram_0_avalon_sram_slave_end_xfer & (~sram_0_avalon_sram_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //sram_0_avalon_sram_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign sram_0_avalon_sram_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_sram_0_avalon_sram_slave & sram_0_avalon_sram_slave_allgrants) | (end_xfer_arb_share_counter_term_sram_0_avalon_sram_slave & ~sram_0_avalon_sram_slave_non_bursting_master_requests);

  //sram_0_avalon_sram_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_0_avalon_sram_slave_arb_share_counter <= 0;
      else if (sram_0_avalon_sram_slave_arb_counter_enable)
          sram_0_avalon_sram_slave_arb_share_counter <= sram_0_avalon_sram_slave_arb_share_counter_next_value;
    end


  //sram_0_avalon_sram_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_0_avalon_sram_slave_slavearbiterlockenable <= 0;
      else if ((|sram_0_avalon_sram_slave_master_qreq_vector & end_xfer_arb_share_counter_term_sram_0_avalon_sram_slave) | (end_xfer_arb_share_counter_term_sram_0_avalon_sram_slave & ~sram_0_avalon_sram_slave_non_bursting_master_requests))
          sram_0_avalon_sram_slave_slavearbiterlockenable <= |sram_0_avalon_sram_slave_arb_share_counter_next_value;
    end


  //cpu/data_master sram_0/avalon_sram_slave arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = sram_0_avalon_sram_slave_slavearbiterlockenable & cpu_data_master_continuerequest;

  //sram_0_avalon_sram_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign sram_0_avalon_sram_slave_slavearbiterlockenable2 = |sram_0_avalon_sram_slave_arb_share_counter_next_value;

  //cpu/data_master sram_0/avalon_sram_slave arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = sram_0_avalon_sram_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //cpu/instruction_master sram_0/avalon_sram_slave arbiterlock, which is an e_assign
  assign cpu_instruction_master_arbiterlock = sram_0_avalon_sram_slave_slavearbiterlockenable & cpu_instruction_master_continuerequest;

  //cpu/instruction_master sram_0/avalon_sram_slave arbiterlock2, which is an e_assign
  assign cpu_instruction_master_arbiterlock2 = sram_0_avalon_sram_slave_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;

  //cpu/instruction_master granted sram_0/avalon_sram_slave last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_instruction_master_granted_slave_sram_0_avalon_sram_slave <= 0;
      else if (1)
          last_cycle_cpu_instruction_master_granted_slave_sram_0_avalon_sram_slave <= cpu_instruction_master_saved_grant_sram_0_avalon_sram_slave ? 1 : (sram_0_avalon_sram_slave_arbitration_holdoff_internal | ~cpu_instruction_master_requests_sram_0_avalon_sram_slave) ? 0 : last_cycle_cpu_instruction_master_granted_slave_sram_0_avalon_sram_slave;
    end


  //cpu_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_sram_0_avalon_sram_slave & cpu_instruction_master_requests_sram_0_avalon_sram_slave;

  //sram_0_avalon_sram_slave_any_continuerequest at least one master continues requesting, which is an e_mux
  assign sram_0_avalon_sram_slave_any_continuerequest = cpu_instruction_master_continuerequest |
    cpu_data_master_continuerequest;

  assign cpu_data_master_qualified_request_sram_0_avalon_sram_slave = cpu_data_master_requests_sram_0_avalon_sram_slave & ~((cpu_data_master_read & ((|cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register))) | ((~cpu_data_master_waitrequest | cpu_data_master_no_byte_enables_and_last_term | !cpu_data_master_byteenable_sram_0_avalon_sram_slave) & cpu_data_master_write) | cpu_instruction_master_arbiterlock);
  //cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register_in = cpu_data_master_granted_sram_0_avalon_sram_slave & cpu_data_master_read & ~sram_0_avalon_sram_slave_waits_for_read & ~(|cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register);

  //shift register p1 cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register = {cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register, cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register_in};

  //cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register <= 0;
      else if (1)
          cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register <= p1_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register;
    end


  //local readdatavalid cpu_data_master_read_data_valid_sram_0_avalon_sram_slave, which is an e_mux
  assign cpu_data_master_read_data_valid_sram_0_avalon_sram_slave = cpu_data_master_read_data_valid_sram_0_avalon_sram_slave_shift_register[1];

  //sram_0_avalon_sram_slave_writedata mux, which is an e_mux
  assign sram_0_avalon_sram_slave_writedata = cpu_data_master_dbs_write_16;

  assign cpu_instruction_master_requests_sram_0_avalon_sram_slave = (({cpu_instruction_master_address_to_slave[23 : 19] , 19'b0} == 24'h0) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
  //cpu/data_master granted sram_0/avalon_sram_slave last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_data_master_granted_slave_sram_0_avalon_sram_slave <= 0;
      else if (1)
          last_cycle_cpu_data_master_granted_slave_sram_0_avalon_sram_slave <= cpu_data_master_saved_grant_sram_0_avalon_sram_slave ? 1 : (sram_0_avalon_sram_slave_arbitration_holdoff_internal | ~cpu_data_master_requests_sram_0_avalon_sram_slave) ? 0 : last_cycle_cpu_data_master_granted_slave_sram_0_avalon_sram_slave;
    end


  //cpu_data_master_continuerequest continued request, which is an e_mux
  assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_sram_0_avalon_sram_slave & cpu_data_master_requests_sram_0_avalon_sram_slave;

  assign cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave = cpu_instruction_master_requests_sram_0_avalon_sram_slave & ~((cpu_instruction_master_read & ((2 < cpu_instruction_master_latency_counter))) | cpu_data_master_arbiterlock);
  //cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register_in = cpu_instruction_master_granted_sram_0_avalon_sram_slave & cpu_instruction_master_read & ~sram_0_avalon_sram_slave_waits_for_read;

  //shift register p1 cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register = {cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register, cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register_in};

  //cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register <= 0;
      else if (1)
          cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register <= p1_cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register;
    end


  //local readdatavalid cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave, which is an e_mux
  assign cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave = cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave_shift_register[1];

  //allow new arb cycle for sram_0/avalon_sram_slave, which is an e_assign
  assign sram_0_avalon_sram_slave_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;

  //cpu/instruction_master assignment into master qualified-requests vector for sram_0/avalon_sram_slave, which is an e_assign
  assign sram_0_avalon_sram_slave_master_qreq_vector[0] = cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave;

  //cpu/instruction_master grant sram_0/avalon_sram_slave, which is an e_assign
  assign cpu_instruction_master_granted_sram_0_avalon_sram_slave = sram_0_avalon_sram_slave_grant_vector[0];

  //cpu/instruction_master saved-grant sram_0/avalon_sram_slave, which is an e_assign
  assign cpu_instruction_master_saved_grant_sram_0_avalon_sram_slave = sram_0_avalon_sram_slave_arb_winner[0] && cpu_instruction_master_requests_sram_0_avalon_sram_slave;

  //cpu/data_master assignment into master qualified-requests vector for sram_0/avalon_sram_slave, which is an e_assign
  assign sram_0_avalon_sram_slave_master_qreq_vector[1] = cpu_data_master_qualified_request_sram_0_avalon_sram_slave;

  //cpu/data_master grant sram_0/avalon_sram_slave, which is an e_assign
  assign cpu_data_master_granted_sram_0_avalon_sram_slave = sram_0_avalon_sram_slave_grant_vector[1];

  //cpu/data_master saved-grant sram_0/avalon_sram_slave, which is an e_assign
  assign cpu_data_master_saved_grant_sram_0_avalon_sram_slave = sram_0_avalon_sram_slave_arb_winner[1] && cpu_data_master_requests_sram_0_avalon_sram_slave;

  //sram_0/avalon_sram_slave chosen-master double-vector, which is an e_assign
  assign sram_0_avalon_sram_slave_chosen_master_double_vector = {sram_0_avalon_sram_slave_master_qreq_vector, sram_0_avalon_sram_slave_master_qreq_vector} & ({~sram_0_avalon_sram_slave_master_qreq_vector, ~sram_0_avalon_sram_slave_master_qreq_vector} + sram_0_avalon_sram_slave_arb_addend);

  //stable onehot encoding of arb winner
  assign sram_0_avalon_sram_slave_arb_winner = (sram_0_avalon_sram_slave_allow_new_arb_cycle & | sram_0_avalon_sram_slave_grant_vector) ? sram_0_avalon_sram_slave_grant_vector : sram_0_avalon_sram_slave_saved_chosen_master_vector;

  //saved sram_0_avalon_sram_slave_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_0_avalon_sram_slave_saved_chosen_master_vector <= 0;
      else if (sram_0_avalon_sram_slave_allow_new_arb_cycle)
          sram_0_avalon_sram_slave_saved_chosen_master_vector <= |sram_0_avalon_sram_slave_grant_vector ? sram_0_avalon_sram_slave_grant_vector : sram_0_avalon_sram_slave_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign sram_0_avalon_sram_slave_grant_vector = {(sram_0_avalon_sram_slave_chosen_master_double_vector[1] | sram_0_avalon_sram_slave_chosen_master_double_vector[3]),
    (sram_0_avalon_sram_slave_chosen_master_double_vector[0] | sram_0_avalon_sram_slave_chosen_master_double_vector[2])};

  //sram_0/avalon_sram_slave chosen master rotated left, which is an e_assign
  assign sram_0_avalon_sram_slave_chosen_master_rot_left = (sram_0_avalon_sram_slave_arb_winner << 1) ? (sram_0_avalon_sram_slave_arb_winner << 1) : 1;

  //sram_0/avalon_sram_slave's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_0_avalon_sram_slave_arb_addend <= 1;
      else if (|sram_0_avalon_sram_slave_grant_vector)
          sram_0_avalon_sram_slave_arb_addend <= sram_0_avalon_sram_slave_end_xfer? sram_0_avalon_sram_slave_chosen_master_rot_left : sram_0_avalon_sram_slave_grant_vector;
    end


  assign sram_0_avalon_sram_slave_chipselect = cpu_data_master_granted_sram_0_avalon_sram_slave | cpu_instruction_master_granted_sram_0_avalon_sram_slave;
  //sram_0_avalon_sram_slave_firsttransfer first transaction, which is an e_assign
  assign sram_0_avalon_sram_slave_firsttransfer = sram_0_avalon_sram_slave_begins_xfer ? sram_0_avalon_sram_slave_unreg_firsttransfer : sram_0_avalon_sram_slave_reg_firsttransfer;

  //sram_0_avalon_sram_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign sram_0_avalon_sram_slave_unreg_firsttransfer = ~(sram_0_avalon_sram_slave_slavearbiterlockenable & sram_0_avalon_sram_slave_any_continuerequest);

  //sram_0_avalon_sram_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sram_0_avalon_sram_slave_reg_firsttransfer <= 1'b1;
      else if (sram_0_avalon_sram_slave_begins_xfer)
          sram_0_avalon_sram_slave_reg_firsttransfer <= sram_0_avalon_sram_slave_unreg_firsttransfer;
    end


  //sram_0_avalon_sram_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign sram_0_avalon_sram_slave_beginbursttransfer_internal = sram_0_avalon_sram_slave_begins_xfer;

  //sram_0_avalon_sram_slave_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign sram_0_avalon_sram_slave_arbitration_holdoff_internal = sram_0_avalon_sram_slave_begins_xfer & sram_0_avalon_sram_slave_firsttransfer;

  //sram_0_avalon_sram_slave_read assignment, which is an e_mux
  assign sram_0_avalon_sram_slave_read = (cpu_data_master_granted_sram_0_avalon_sram_slave & cpu_data_master_read) | (cpu_instruction_master_granted_sram_0_avalon_sram_slave & cpu_instruction_master_read);

  //sram_0_avalon_sram_slave_write assignment, which is an e_mux
  assign sram_0_avalon_sram_slave_write = cpu_data_master_granted_sram_0_avalon_sram_slave & cpu_data_master_write;

  assign shifted_address_to_sram_0_avalon_sram_slave_from_cpu_data_master = {cpu_data_master_address_to_slave >> 2,
    cpu_data_master_dbs_address[1],
    {1 {1'b0}}};

  //sram_0_avalon_sram_slave_address mux, which is an e_mux
  assign sram_0_avalon_sram_slave_address = (cpu_data_master_granted_sram_0_avalon_sram_slave)? (shifted_address_to_sram_0_avalon_sram_slave_from_cpu_data_master >> 1) :
    (shifted_address_to_sram_0_avalon_sram_slave_from_cpu_instruction_master >> 1);

  assign shifted_address_to_sram_0_avalon_sram_slave_from_cpu_instruction_master = {cpu_instruction_master_address_to_slave >> 2,
    cpu_instruction_master_dbs_address[1],
    {1 {1'b0}}};

  //d1_sram_0_avalon_sram_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_sram_0_avalon_sram_slave_end_xfer <= 1;
      else if (1)
          d1_sram_0_avalon_sram_slave_end_xfer <= sram_0_avalon_sram_slave_end_xfer;
    end


  //sram_0_avalon_sram_slave_waits_for_read in a cycle, which is an e_mux
  assign sram_0_avalon_sram_slave_waits_for_read = sram_0_avalon_sram_slave_in_a_read_cycle & 0;

  //sram_0_avalon_sram_slave_in_a_read_cycle assignment, which is an e_assign
  assign sram_0_avalon_sram_slave_in_a_read_cycle = (cpu_data_master_granted_sram_0_avalon_sram_slave & cpu_data_master_read) | (cpu_instruction_master_granted_sram_0_avalon_sram_slave & cpu_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = sram_0_avalon_sram_slave_in_a_read_cycle;

  //sram_0_avalon_sram_slave_waits_for_write in a cycle, which is an e_mux
  assign sram_0_avalon_sram_slave_waits_for_write = sram_0_avalon_sram_slave_in_a_write_cycle & 0;

  //sram_0_avalon_sram_slave_in_a_write_cycle assignment, which is an e_assign
  assign sram_0_avalon_sram_slave_in_a_write_cycle = cpu_data_master_granted_sram_0_avalon_sram_slave & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = sram_0_avalon_sram_slave_in_a_write_cycle;

  assign wait_for_sram_0_avalon_sram_slave_counter = 0;
  //sram_0_avalon_sram_slave_byteenable byte enable port mux, which is an e_mux
  assign sram_0_avalon_sram_slave_byteenable = (cpu_data_master_granted_sram_0_avalon_sram_slave)? cpu_data_master_byteenable_sram_0_avalon_sram_slave :
    -1;

  assign {cpu_data_master_byteenable_sram_0_avalon_sram_slave_segment_1,
cpu_data_master_byteenable_sram_0_avalon_sram_slave_segment_0} = cpu_data_master_byteenable;
  assign cpu_data_master_byteenable_sram_0_avalon_sram_slave = ((cpu_data_master_dbs_address[1] == 0))? cpu_data_master_byteenable_sram_0_avalon_sram_slave_segment_0 :
    cpu_data_master_byteenable_sram_0_avalon_sram_slave_segment_1;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //sram_0/avalon_sram_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_granted_sram_0_avalon_sram_slave + cpu_instruction_master_granted_sram_0_avalon_sram_slave > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_saved_grant_sram_0_avalon_sram_slave + cpu_instruction_master_saved_grant_sram_0_avalon_sram_slave > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module sysid_control_slave_arbitrator (
                                        // inputs:
                                         clk,
                                         cpu_data_master_address_to_slave,
                                         cpu_data_master_read,
                                         cpu_data_master_write,
                                         reset_n,
                                         sysid_control_slave_readdata,

                                        // outputs:
                                         cpu_data_master_granted_sysid_control_slave,
                                         cpu_data_master_qualified_request_sysid_control_slave,
                                         cpu_data_master_read_data_valid_sysid_control_slave,
                                         cpu_data_master_requests_sysid_control_slave,
                                         d1_sysid_control_slave_end_xfer,
                                         sysid_control_slave_address,
                                         sysid_control_slave_readdata_from_sa
                                      )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output           cpu_data_master_granted_sysid_control_slave;
  output           cpu_data_master_qualified_request_sysid_control_slave;
  output           cpu_data_master_read_data_valid_sysid_control_slave;
  output           cpu_data_master_requests_sysid_control_slave;
  output           d1_sysid_control_slave_end_xfer;
  output           sysid_control_slave_address;
  output  [ 31: 0] sysid_control_slave_readdata_from_sa;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_write;
  input            reset_n;
  input   [ 31: 0] sysid_control_slave_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_sysid_control_slave;
  wire             cpu_data_master_qualified_request_sysid_control_slave;
  wire             cpu_data_master_read_data_valid_sysid_control_slave;
  wire             cpu_data_master_requests_sysid_control_slave;
  wire             cpu_data_master_saved_grant_sysid_control_slave;
  reg              d1_reasons_to_wait;
  reg              d1_sysid_control_slave_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_sysid_control_slave;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 23: 0] shifted_address_to_sysid_control_slave_from_cpu_data_master;
  wire             sysid_control_slave_address;
  wire             sysid_control_slave_allgrants;
  wire             sysid_control_slave_allow_new_arb_cycle;
  wire             sysid_control_slave_any_bursting_master_saved_grant;
  wire             sysid_control_slave_any_continuerequest;
  wire             sysid_control_slave_arb_counter_enable;
  reg     [  2: 0] sysid_control_slave_arb_share_counter;
  wire    [  2: 0] sysid_control_slave_arb_share_counter_next_value;
  wire    [  2: 0] sysid_control_slave_arb_share_set_values;
  wire             sysid_control_slave_beginbursttransfer_internal;
  wire             sysid_control_slave_begins_xfer;
  wire             sysid_control_slave_end_xfer;
  wire             sysid_control_slave_firsttransfer;
  wire             sysid_control_slave_grant_vector;
  wire             sysid_control_slave_in_a_read_cycle;
  wire             sysid_control_slave_in_a_write_cycle;
  wire             sysid_control_slave_master_qreq_vector;
  wire             sysid_control_slave_non_bursting_master_requests;
  wire    [ 31: 0] sysid_control_slave_readdata_from_sa;
  reg              sysid_control_slave_reg_firsttransfer;
  reg              sysid_control_slave_slavearbiterlockenable;
  wire             sysid_control_slave_slavearbiterlockenable2;
  wire             sysid_control_slave_unreg_firsttransfer;
  wire             sysid_control_slave_waits_for_read;
  wire             sysid_control_slave_waits_for_write;
  wire             wait_for_sysid_control_slave_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~sysid_control_slave_end_xfer;
    end


  assign sysid_control_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_sysid_control_slave));
  //assign sysid_control_slave_readdata_from_sa = sysid_control_slave_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign sysid_control_slave_readdata_from_sa = sysid_control_slave_readdata;

  assign cpu_data_master_requests_sysid_control_slave = (({cpu_data_master_address_to_slave[23 : 3] , 3'b0} == 24'h810a8) & (cpu_data_master_read | cpu_data_master_write)) & cpu_data_master_read;
  //sysid_control_slave_arb_share_counter set values, which is an e_mux
  assign sysid_control_slave_arb_share_set_values = 1;

  //sysid_control_slave_non_bursting_master_requests mux, which is an e_mux
  assign sysid_control_slave_non_bursting_master_requests = cpu_data_master_requests_sysid_control_slave;

  //sysid_control_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign sysid_control_slave_any_bursting_master_saved_grant = 0;

  //sysid_control_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign sysid_control_slave_arb_share_counter_next_value = sysid_control_slave_firsttransfer ? (sysid_control_slave_arb_share_set_values - 1) : |sysid_control_slave_arb_share_counter ? (sysid_control_slave_arb_share_counter - 1) : 0;

  //sysid_control_slave_allgrants all slave grants, which is an e_mux
  assign sysid_control_slave_allgrants = |sysid_control_slave_grant_vector;

  //sysid_control_slave_end_xfer assignment, which is an e_assign
  assign sysid_control_slave_end_xfer = ~(sysid_control_slave_waits_for_read | sysid_control_slave_waits_for_write);

  //end_xfer_arb_share_counter_term_sysid_control_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_sysid_control_slave = sysid_control_slave_end_xfer & (~sysid_control_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //sysid_control_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign sysid_control_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_sysid_control_slave & sysid_control_slave_allgrants) | (end_xfer_arb_share_counter_term_sysid_control_slave & ~sysid_control_slave_non_bursting_master_requests);

  //sysid_control_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sysid_control_slave_arb_share_counter <= 0;
      else if (sysid_control_slave_arb_counter_enable)
          sysid_control_slave_arb_share_counter <= sysid_control_slave_arb_share_counter_next_value;
    end


  //sysid_control_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sysid_control_slave_slavearbiterlockenable <= 0;
      else if ((|sysid_control_slave_master_qreq_vector & end_xfer_arb_share_counter_term_sysid_control_slave) | (end_xfer_arb_share_counter_term_sysid_control_slave & ~sysid_control_slave_non_bursting_master_requests))
          sysid_control_slave_slavearbiterlockenable <= |sysid_control_slave_arb_share_counter_next_value;
    end


  //cpu/data_master sysid/control_slave arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = sysid_control_slave_slavearbiterlockenable & cpu_data_master_continuerequest;

  //sysid_control_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign sysid_control_slave_slavearbiterlockenable2 = |sysid_control_slave_arb_share_counter_next_value;

  //cpu/data_master sysid/control_slave arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = sysid_control_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //sysid_control_slave_any_continuerequest at least one master continues requesting, which is an e_assign
  assign sysid_control_slave_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_sysid_control_slave = cpu_data_master_requests_sysid_control_slave;
  //master is always granted when requested
  assign cpu_data_master_granted_sysid_control_slave = cpu_data_master_qualified_request_sysid_control_slave;

  //cpu/data_master saved-grant sysid/control_slave, which is an e_assign
  assign cpu_data_master_saved_grant_sysid_control_slave = cpu_data_master_requests_sysid_control_slave;

  //allow new arb cycle for sysid/control_slave, which is an e_assign
  assign sysid_control_slave_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign sysid_control_slave_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign sysid_control_slave_master_qreq_vector = 1;

  //sysid_control_slave_firsttransfer first transaction, which is an e_assign
  assign sysid_control_slave_firsttransfer = sysid_control_slave_begins_xfer ? sysid_control_slave_unreg_firsttransfer : sysid_control_slave_reg_firsttransfer;

  //sysid_control_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign sysid_control_slave_unreg_firsttransfer = ~(sysid_control_slave_slavearbiterlockenable & sysid_control_slave_any_continuerequest);

  //sysid_control_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          sysid_control_slave_reg_firsttransfer <= 1'b1;
      else if (sysid_control_slave_begins_xfer)
          sysid_control_slave_reg_firsttransfer <= sysid_control_slave_unreg_firsttransfer;
    end


  //sysid_control_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign sysid_control_slave_beginbursttransfer_internal = sysid_control_slave_begins_xfer;

  assign shifted_address_to_sysid_control_slave_from_cpu_data_master = cpu_data_master_address_to_slave;
  //sysid_control_slave_address mux, which is an e_mux
  assign sysid_control_slave_address = shifted_address_to_sysid_control_slave_from_cpu_data_master >> 2;

  //d1_sysid_control_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_sysid_control_slave_end_xfer <= 1;
      else if (1)
          d1_sysid_control_slave_end_xfer <= sysid_control_slave_end_xfer;
    end


  //sysid_control_slave_waits_for_read in a cycle, which is an e_mux
  assign sysid_control_slave_waits_for_read = sysid_control_slave_in_a_read_cycle & sysid_control_slave_begins_xfer;

  //sysid_control_slave_in_a_read_cycle assignment, which is an e_assign
  assign sysid_control_slave_in_a_read_cycle = cpu_data_master_granted_sysid_control_slave & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = sysid_control_slave_in_a_read_cycle;

  //sysid_control_slave_waits_for_write in a cycle, which is an e_mux
  assign sysid_control_slave_waits_for_write = sysid_control_slave_in_a_write_cycle & 0;

  //sysid_control_slave_in_a_write_cycle assignment, which is an e_assign
  assign sysid_control_slave_in_a_write_cycle = cpu_data_master_granted_sysid_control_slave & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = sysid_control_slave_in_a_write_cycle;

  assign wait_for_sysid_control_slave_counter = 0;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //sysid/control_slave enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module timer_s1_arbitrator (
                             // inputs:
                              clk,
                              cpu_data_master_address_to_slave,
                              cpu_data_master_read,
                              cpu_data_master_waitrequest,
                              cpu_data_master_write,
                              cpu_data_master_writedata,
                              reset_n,
                              timer_s1_irq,
                              timer_s1_readdata,

                             // outputs:
                              cpu_data_master_granted_timer_s1,
                              cpu_data_master_qualified_request_timer_s1,
                              cpu_data_master_read_data_valid_timer_s1,
                              cpu_data_master_requests_timer_s1,
                              d1_timer_s1_end_xfer,
                              timer_s1_address,
                              timer_s1_chipselect,
                              timer_s1_irq_from_sa,
                              timer_s1_readdata_from_sa,
                              timer_s1_reset_n,
                              timer_s1_write_n,
                              timer_s1_writedata
                           )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output           cpu_data_master_granted_timer_s1;
  output           cpu_data_master_qualified_request_timer_s1;
  output           cpu_data_master_read_data_valid_timer_s1;
  output           cpu_data_master_requests_timer_s1;
  output           d1_timer_s1_end_xfer;
  output  [  2: 0] timer_s1_address;
  output           timer_s1_chipselect;
  output           timer_s1_irq_from_sa;
  output  [ 15: 0] timer_s1_readdata_from_sa;
  output           timer_s1_reset_n;
  output           timer_s1_write_n;
  output  [ 15: 0] timer_s1_writedata;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 31: 0] cpu_data_master_writedata;
  input            reset_n;
  input            timer_s1_irq;
  input   [ 15: 0] timer_s1_readdata;

  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_timer_s1;
  wire             cpu_data_master_qualified_request_timer_s1;
  wire             cpu_data_master_read_data_valid_timer_s1;
  wire             cpu_data_master_requests_timer_s1;
  wire             cpu_data_master_saved_grant_timer_s1;
  reg              d1_reasons_to_wait;
  reg              d1_timer_s1_end_xfer;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_timer_s1;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  wire    [ 23: 0] shifted_address_to_timer_s1_from_cpu_data_master;
  wire    [  2: 0] timer_s1_address;
  wire             timer_s1_allgrants;
  wire             timer_s1_allow_new_arb_cycle;
  wire             timer_s1_any_bursting_master_saved_grant;
  wire             timer_s1_any_continuerequest;
  wire             timer_s1_arb_counter_enable;
  reg     [  2: 0] timer_s1_arb_share_counter;
  wire    [  2: 0] timer_s1_arb_share_counter_next_value;
  wire    [  2: 0] timer_s1_arb_share_set_values;
  wire             timer_s1_beginbursttransfer_internal;
  wire             timer_s1_begins_xfer;
  wire             timer_s1_chipselect;
  wire             timer_s1_end_xfer;
  wire             timer_s1_firsttransfer;
  wire             timer_s1_grant_vector;
  wire             timer_s1_in_a_read_cycle;
  wire             timer_s1_in_a_write_cycle;
  wire             timer_s1_irq_from_sa;
  wire             timer_s1_master_qreq_vector;
  wire             timer_s1_non_bursting_master_requests;
  wire    [ 15: 0] timer_s1_readdata_from_sa;
  reg              timer_s1_reg_firsttransfer;
  wire             timer_s1_reset_n;
  reg              timer_s1_slavearbiterlockenable;
  wire             timer_s1_slavearbiterlockenable2;
  wire             timer_s1_unreg_firsttransfer;
  wire             timer_s1_waits_for_read;
  wire             timer_s1_waits_for_write;
  wire             timer_s1_write_n;
  wire    [ 15: 0] timer_s1_writedata;
  wire             wait_for_timer_s1_counter;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~timer_s1_end_xfer;
    end


  assign timer_s1_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_timer_s1));
  //assign timer_s1_readdata_from_sa = timer_s1_readdata so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign timer_s1_readdata_from_sa = timer_s1_readdata;

  assign cpu_data_master_requests_timer_s1 = ({cpu_data_master_address_to_slave[23 : 5] , 5'b0} == 24'h81000) & (cpu_data_master_read | cpu_data_master_write);
  //timer_s1_arb_share_counter set values, which is an e_mux
  assign timer_s1_arb_share_set_values = 1;

  //timer_s1_non_bursting_master_requests mux, which is an e_mux
  assign timer_s1_non_bursting_master_requests = cpu_data_master_requests_timer_s1;

  //timer_s1_any_bursting_master_saved_grant mux, which is an e_mux
  assign timer_s1_any_bursting_master_saved_grant = 0;

  //timer_s1_arb_share_counter_next_value assignment, which is an e_assign
  assign timer_s1_arb_share_counter_next_value = timer_s1_firsttransfer ? (timer_s1_arb_share_set_values - 1) : |timer_s1_arb_share_counter ? (timer_s1_arb_share_counter - 1) : 0;

  //timer_s1_allgrants all slave grants, which is an e_mux
  assign timer_s1_allgrants = |timer_s1_grant_vector;

  //timer_s1_end_xfer assignment, which is an e_assign
  assign timer_s1_end_xfer = ~(timer_s1_waits_for_read | timer_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_timer_s1 arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_timer_s1 = timer_s1_end_xfer & (~timer_s1_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //timer_s1_arb_share_counter arbitration counter enable, which is an e_assign
  assign timer_s1_arb_counter_enable = (end_xfer_arb_share_counter_term_timer_s1 & timer_s1_allgrants) | (end_xfer_arb_share_counter_term_timer_s1 & ~timer_s1_non_bursting_master_requests);

  //timer_s1_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          timer_s1_arb_share_counter <= 0;
      else if (timer_s1_arb_counter_enable)
          timer_s1_arb_share_counter <= timer_s1_arb_share_counter_next_value;
    end


  //timer_s1_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          timer_s1_slavearbiterlockenable <= 0;
      else if ((|timer_s1_master_qreq_vector & end_xfer_arb_share_counter_term_timer_s1) | (end_xfer_arb_share_counter_term_timer_s1 & ~timer_s1_non_bursting_master_requests))
          timer_s1_slavearbiterlockenable <= |timer_s1_arb_share_counter_next_value;
    end


  //cpu/data_master timer/s1 arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = timer_s1_slavearbiterlockenable & cpu_data_master_continuerequest;

  //timer_s1_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign timer_s1_slavearbiterlockenable2 = |timer_s1_arb_share_counter_next_value;

  //cpu/data_master timer/s1 arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = timer_s1_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //timer_s1_any_continuerequest at least one master continues requesting, which is an e_assign
  assign timer_s1_any_continuerequest = 1;

  //cpu_data_master_continuerequest continued request, which is an e_assign
  assign cpu_data_master_continuerequest = 1;

  assign cpu_data_master_qualified_request_timer_s1 = cpu_data_master_requests_timer_s1 & ~(((~cpu_data_master_waitrequest) & cpu_data_master_write));
  //timer_s1_writedata mux, which is an e_mux
  assign timer_s1_writedata = cpu_data_master_writedata;

  //master is always granted when requested
  assign cpu_data_master_granted_timer_s1 = cpu_data_master_qualified_request_timer_s1;

  //cpu/data_master saved-grant timer/s1, which is an e_assign
  assign cpu_data_master_saved_grant_timer_s1 = cpu_data_master_requests_timer_s1;

  //allow new arb cycle for timer/s1, which is an e_assign
  assign timer_s1_allow_new_arb_cycle = 1;

  //placeholder chosen master
  assign timer_s1_grant_vector = 1;

  //placeholder vector of master qualified-requests
  assign timer_s1_master_qreq_vector = 1;

  //timer_s1_reset_n assignment, which is an e_assign
  assign timer_s1_reset_n = reset_n;

  assign timer_s1_chipselect = cpu_data_master_granted_timer_s1;
  //timer_s1_firsttransfer first transaction, which is an e_assign
  assign timer_s1_firsttransfer = timer_s1_begins_xfer ? timer_s1_unreg_firsttransfer : timer_s1_reg_firsttransfer;

  //timer_s1_unreg_firsttransfer first transaction, which is an e_assign
  assign timer_s1_unreg_firsttransfer = ~(timer_s1_slavearbiterlockenable & timer_s1_any_continuerequest);

  //timer_s1_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          timer_s1_reg_firsttransfer <= 1'b1;
      else if (timer_s1_begins_xfer)
          timer_s1_reg_firsttransfer <= timer_s1_unreg_firsttransfer;
    end


  //timer_s1_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign timer_s1_beginbursttransfer_internal = timer_s1_begins_xfer;

  //~timer_s1_write_n assignment, which is an e_mux
  assign timer_s1_write_n = ~(cpu_data_master_granted_timer_s1 & cpu_data_master_write);

  assign shifted_address_to_timer_s1_from_cpu_data_master = cpu_data_master_address_to_slave;
  //timer_s1_address mux, which is an e_mux
  assign timer_s1_address = shifted_address_to_timer_s1_from_cpu_data_master >> 2;

  //d1_timer_s1_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_timer_s1_end_xfer <= 1;
      else if (1)
          d1_timer_s1_end_xfer <= timer_s1_end_xfer;
    end


  //timer_s1_waits_for_read in a cycle, which is an e_mux
  assign timer_s1_waits_for_read = timer_s1_in_a_read_cycle & timer_s1_begins_xfer;

  //timer_s1_in_a_read_cycle assignment, which is an e_assign
  assign timer_s1_in_a_read_cycle = cpu_data_master_granted_timer_s1 & cpu_data_master_read;

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = timer_s1_in_a_read_cycle;

  //timer_s1_waits_for_write in a cycle, which is an e_mux
  assign timer_s1_waits_for_write = timer_s1_in_a_write_cycle & 0;

  //timer_s1_in_a_write_cycle assignment, which is an e_assign
  assign timer_s1_in_a_write_cycle = cpu_data_master_granted_timer_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = timer_s1_in_a_write_cycle;

  assign wait_for_timer_s1_counter = 0;
  //assign timer_s1_irq_from_sa = timer_s1_irq so that symbol knows where to group signals which may go to master only, which is an e_assign
  assign timer_s1_irq_from_sa = timer_s1_irq;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //timer/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module tristate_bridge_avalon_slave_arbitrator (
                                                 // inputs:
                                                  clk,
                                                  cpu_data_master_address_to_slave,
                                                  cpu_data_master_byteenable,
                                                  cpu_data_master_dbs_address,
                                                  cpu_data_master_dbs_write_8,
                                                  cpu_data_master_no_byte_enables_and_last_term,
                                                  cpu_data_master_read,
                                                  cpu_data_master_waitrequest,
                                                  cpu_data_master_write,
                                                  cpu_instruction_master_address_to_slave,
                                                  cpu_instruction_master_dbs_address,
                                                  cpu_instruction_master_latency_counter,
                                                  cpu_instruction_master_read,
                                                  reset_n,

                                                 // outputs:
                                                  address_to_the_flash,
                                                  cpu_data_master_byteenable_flash_s1,
                                                  cpu_data_master_granted_flash_s1,
                                                  cpu_data_master_qualified_request_flash_s1,
                                                  cpu_data_master_read_data_valid_flash_s1,
                                                  cpu_data_master_requests_flash_s1,
                                                  cpu_instruction_master_granted_flash_s1,
                                                  cpu_instruction_master_qualified_request_flash_s1,
                                                  cpu_instruction_master_read_data_valid_flash_s1,
                                                  cpu_instruction_master_requests_flash_s1,
                                                  d1_tristate_bridge_avalon_slave_end_xfer,
                                                  data_to_and_from_the_flash,
                                                  incoming_data_to_and_from_the_flash,
                                                  incoming_data_to_and_from_the_flash_with_Xs_converted_to_0,
                                                  read_n_to_the_flash,
                                                  registered_cpu_data_master_read_data_valid_flash_s1,
                                                  select_n_to_the_flash,
                                                  write_n_to_the_flash
                                               )
  /* synthesis auto_dissolve = "FALSE" */ ;

  output  [ 21: 0] address_to_the_flash;
  output           cpu_data_master_byteenable_flash_s1;
  output           cpu_data_master_granted_flash_s1;
  output           cpu_data_master_qualified_request_flash_s1;
  output           cpu_data_master_read_data_valid_flash_s1;
  output           cpu_data_master_requests_flash_s1;
  output           cpu_instruction_master_granted_flash_s1;
  output           cpu_instruction_master_qualified_request_flash_s1;
  output           cpu_instruction_master_read_data_valid_flash_s1;
  output           cpu_instruction_master_requests_flash_s1;
  output           d1_tristate_bridge_avalon_slave_end_xfer;
  inout   [  7: 0] data_to_and_from_the_flash;
  output  [  7: 0] incoming_data_to_and_from_the_flash;
  output  [  7: 0] incoming_data_to_and_from_the_flash_with_Xs_converted_to_0;
  output           read_n_to_the_flash;
  output           registered_cpu_data_master_read_data_valid_flash_s1;
  output           select_n_to_the_flash;
  output           write_n_to_the_flash;
  input            clk;
  input   [ 23: 0] cpu_data_master_address_to_slave;
  input   [  3: 0] cpu_data_master_byteenable;
  input   [  1: 0] cpu_data_master_dbs_address;
  input   [  7: 0] cpu_data_master_dbs_write_8;
  input            cpu_data_master_no_byte_enables_and_last_term;
  input            cpu_data_master_read;
  input            cpu_data_master_waitrequest;
  input            cpu_data_master_write;
  input   [ 23: 0] cpu_instruction_master_address_to_slave;
  input   [  1: 0] cpu_instruction_master_dbs_address;
  input   [  1: 0] cpu_instruction_master_latency_counter;
  input            cpu_instruction_master_read;
  input            reset_n;

  reg     [ 21: 0] address_to_the_flash /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  wire             cpu_data_master_arbiterlock;
  wire             cpu_data_master_arbiterlock2;
  wire             cpu_data_master_byteenable_flash_s1;
  wire             cpu_data_master_byteenable_flash_s1_segment_0;
  wire             cpu_data_master_byteenable_flash_s1_segment_1;
  wire             cpu_data_master_byteenable_flash_s1_segment_2;
  wire             cpu_data_master_byteenable_flash_s1_segment_3;
  wire             cpu_data_master_continuerequest;
  wire             cpu_data_master_granted_flash_s1;
  wire             cpu_data_master_qualified_request_flash_s1;
  wire             cpu_data_master_read_data_valid_flash_s1;
  reg     [  1: 0] cpu_data_master_read_data_valid_flash_s1_shift_register;
  wire             cpu_data_master_read_data_valid_flash_s1_shift_register_in;
  wire             cpu_data_master_requests_flash_s1;
  wire             cpu_data_master_saved_grant_flash_s1;
  wire             cpu_instruction_master_arbiterlock;
  wire             cpu_instruction_master_arbiterlock2;
  wire             cpu_instruction_master_continuerequest;
  wire             cpu_instruction_master_granted_flash_s1;
  wire             cpu_instruction_master_qualified_request_flash_s1;
  wire             cpu_instruction_master_read_data_valid_flash_s1;
  reg     [  1: 0] cpu_instruction_master_read_data_valid_flash_s1_shift_register;
  wire             cpu_instruction_master_read_data_valid_flash_s1_shift_register_in;
  wire             cpu_instruction_master_requests_flash_s1;
  wire             cpu_instruction_master_saved_grant_flash_s1;
  reg              d1_in_a_write_cycle /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_ENABLE_REGISTER=ON"  */;
  reg     [  7: 0] d1_outgoing_data_to_and_from_the_flash /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  reg              d1_reasons_to_wait;
  reg              d1_tristate_bridge_avalon_slave_end_xfer;
  wire    [  7: 0] data_to_and_from_the_flash;
  reg              enable_nonzero_assertions;
  wire             end_xfer_arb_share_counter_term_tristate_bridge_avalon_slave;
  wire             flash_s1_in_a_read_cycle;
  wire             flash_s1_in_a_write_cycle;
  wire             flash_s1_pretend_byte_enable;
  wire             flash_s1_waits_for_read;
  wire             flash_s1_waits_for_write;
  wire             flash_s1_with_write_latency;
  wire             in_a_read_cycle;
  wire             in_a_write_cycle;
  reg     [  7: 0] incoming_data_to_and_from_the_flash /* synthesis ALTERA_ATTRIBUTE = "FAST_INPUT_REGISTER=ON"  */;
  wire             incoming_data_to_and_from_the_flash_bit_0_is_x;
  wire             incoming_data_to_and_from_the_flash_bit_1_is_x;
  wire             incoming_data_to_and_from_the_flash_bit_2_is_x;
  wire             incoming_data_to_and_from_the_flash_bit_3_is_x;
  wire             incoming_data_to_and_from_the_flash_bit_4_is_x;
  wire             incoming_data_to_and_from_the_flash_bit_5_is_x;
  wire             incoming_data_to_and_from_the_flash_bit_6_is_x;
  wire             incoming_data_to_and_from_the_flash_bit_7_is_x;
  wire    [  7: 0] incoming_data_to_and_from_the_flash_with_Xs_converted_to_0;
  reg              last_cycle_cpu_data_master_granted_slave_flash_s1;
  reg              last_cycle_cpu_instruction_master_granted_slave_flash_s1;
  wire    [  7: 0] outgoing_data_to_and_from_the_flash;
  wire    [ 21: 0] p1_address_to_the_flash;
  wire    [  1: 0] p1_cpu_data_master_read_data_valid_flash_s1_shift_register;
  wire    [  1: 0] p1_cpu_instruction_master_read_data_valid_flash_s1_shift_register;
  wire             p1_read_n_to_the_flash;
  wire             p1_select_n_to_the_flash;
  wire             p1_write_n_to_the_flash;
  reg              read_n_to_the_flash /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  wire             registered_cpu_data_master_read_data_valid_flash_s1;
  reg              select_n_to_the_flash /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  wire             time_to_write;
  wire             tristate_bridge_avalon_slave_allgrants;
  wire             tristate_bridge_avalon_slave_allow_new_arb_cycle;
  wire             tristate_bridge_avalon_slave_any_bursting_master_saved_grant;
  wire             tristate_bridge_avalon_slave_any_continuerequest;
  reg     [  1: 0] tristate_bridge_avalon_slave_arb_addend;
  wire             tristate_bridge_avalon_slave_arb_counter_enable;
  reg     [  2: 0] tristate_bridge_avalon_slave_arb_share_counter;
  wire    [  2: 0] tristate_bridge_avalon_slave_arb_share_counter_next_value;
  wire    [  2: 0] tristate_bridge_avalon_slave_arb_share_set_values;
  wire    [  1: 0] tristate_bridge_avalon_slave_arb_winner;
  wire             tristate_bridge_avalon_slave_arbitration_holdoff_internal;
  wire             tristate_bridge_avalon_slave_beginbursttransfer_internal;
  wire             tristate_bridge_avalon_slave_begins_xfer;
  wire    [  3: 0] tristate_bridge_avalon_slave_chosen_master_double_vector;
  wire    [  1: 0] tristate_bridge_avalon_slave_chosen_master_rot_left;
  wire             tristate_bridge_avalon_slave_end_xfer;
  wire             tristate_bridge_avalon_slave_firsttransfer;
  wire    [  1: 0] tristate_bridge_avalon_slave_grant_vector;
  wire    [  1: 0] tristate_bridge_avalon_slave_master_qreq_vector;
  wire             tristate_bridge_avalon_slave_non_bursting_master_requests;
  wire             tristate_bridge_avalon_slave_read_pending;
  reg              tristate_bridge_avalon_slave_reg_firsttransfer;
  reg     [  1: 0] tristate_bridge_avalon_slave_saved_chosen_master_vector;
  reg              tristate_bridge_avalon_slave_slavearbiterlockenable;
  wire             tristate_bridge_avalon_slave_slavearbiterlockenable2;
  wire             tristate_bridge_avalon_slave_unreg_firsttransfer;
  wire             tristate_bridge_avalon_slave_write_pending;
  wire             wait_for_flash_s1_counter;
  reg              write_n_to_the_flash /* synthesis ALTERA_ATTRIBUTE = "FAST_OUTPUT_REGISTER=ON"  */;
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_reasons_to_wait <= 0;
      else if (1)
          d1_reasons_to_wait <= ~tristate_bridge_avalon_slave_end_xfer;
    end


  assign tristate_bridge_avalon_slave_begins_xfer = ~d1_reasons_to_wait & ((cpu_data_master_qualified_request_flash_s1 | cpu_instruction_master_qualified_request_flash_s1));
  assign cpu_data_master_requests_flash_s1 = ({cpu_data_master_address_to_slave[23 : 22] , 22'b0} == 24'h800000) & (cpu_data_master_read | cpu_data_master_write);
  //~select_n_to_the_flash of type chipselect to ~p1_select_n_to_the_flash, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          select_n_to_the_flash <= ~0;
      else if (1)
          select_n_to_the_flash <= p1_select_n_to_the_flash;
    end


  assign tristate_bridge_avalon_slave_write_pending = 0;
  //tristate_bridge/avalon_slave read pending calc, which is an e_assign
  assign tristate_bridge_avalon_slave_read_pending = 0;

  //registered rdv signal_name registered_cpu_data_master_read_data_valid_flash_s1 assignment, which is an e_assign
  assign registered_cpu_data_master_read_data_valid_flash_s1 = cpu_data_master_read_data_valid_flash_s1_shift_register[0];

  //tristate_bridge_avalon_slave_arb_share_counter set values, which is an e_mux
  assign tristate_bridge_avalon_slave_arb_share_set_values = (cpu_data_master_granted_flash_s1)? 4 :
    (cpu_instruction_master_granted_flash_s1)? 4 :
    (cpu_data_master_granted_flash_s1)? 4 :
    (cpu_instruction_master_granted_flash_s1)? 4 :
    1;

  //tristate_bridge_avalon_slave_non_bursting_master_requests mux, which is an e_mux
  assign tristate_bridge_avalon_slave_non_bursting_master_requests = cpu_data_master_requests_flash_s1 |
    cpu_instruction_master_requests_flash_s1 |
    cpu_data_master_requests_flash_s1 |
    cpu_instruction_master_requests_flash_s1;

  //tristate_bridge_avalon_slave_any_bursting_master_saved_grant mux, which is an e_mux
  assign tristate_bridge_avalon_slave_any_bursting_master_saved_grant = 0;

  //tristate_bridge_avalon_slave_arb_share_counter_next_value assignment, which is an e_assign
  assign tristate_bridge_avalon_slave_arb_share_counter_next_value = tristate_bridge_avalon_slave_firsttransfer ? (tristate_bridge_avalon_slave_arb_share_set_values - 1) : |tristate_bridge_avalon_slave_arb_share_counter ? (tristate_bridge_avalon_slave_arb_share_counter - 1) : 0;

  //tristate_bridge_avalon_slave_allgrants all slave grants, which is an e_mux
  assign tristate_bridge_avalon_slave_allgrants = |tristate_bridge_avalon_slave_grant_vector |
    |tristate_bridge_avalon_slave_grant_vector |
    |tristate_bridge_avalon_slave_grant_vector |
    |tristate_bridge_avalon_slave_grant_vector;

  //tristate_bridge_avalon_slave_end_xfer assignment, which is an e_assign
  assign tristate_bridge_avalon_slave_end_xfer = ~(flash_s1_waits_for_read | flash_s1_waits_for_write);

  //end_xfer_arb_share_counter_term_tristate_bridge_avalon_slave arb share counter enable term, which is an e_assign
  assign end_xfer_arb_share_counter_term_tristate_bridge_avalon_slave = tristate_bridge_avalon_slave_end_xfer & (~tristate_bridge_avalon_slave_any_bursting_master_saved_grant | in_a_read_cycle | in_a_write_cycle);

  //tristate_bridge_avalon_slave_arb_share_counter arbitration counter enable, which is an e_assign
  assign tristate_bridge_avalon_slave_arb_counter_enable = (end_xfer_arb_share_counter_term_tristate_bridge_avalon_slave & tristate_bridge_avalon_slave_allgrants) | (end_xfer_arb_share_counter_term_tristate_bridge_avalon_slave & ~tristate_bridge_avalon_slave_non_bursting_master_requests);

  //tristate_bridge_avalon_slave_arb_share_counter counter, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          tristate_bridge_avalon_slave_arb_share_counter <= 0;
      else if (tristate_bridge_avalon_slave_arb_counter_enable)
          tristate_bridge_avalon_slave_arb_share_counter <= tristate_bridge_avalon_slave_arb_share_counter_next_value;
    end


  //tristate_bridge_avalon_slave_slavearbiterlockenable slave enables arbiterlock, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          tristate_bridge_avalon_slave_slavearbiterlockenable <= 0;
      else if ((|tristate_bridge_avalon_slave_master_qreq_vector & end_xfer_arb_share_counter_term_tristate_bridge_avalon_slave) | (end_xfer_arb_share_counter_term_tristate_bridge_avalon_slave & ~tristate_bridge_avalon_slave_non_bursting_master_requests))
          tristate_bridge_avalon_slave_slavearbiterlockenable <= |tristate_bridge_avalon_slave_arb_share_counter_next_value;
    end


  //cpu/data_master tristate_bridge/avalon_slave arbiterlock, which is an e_assign
  assign cpu_data_master_arbiterlock = tristate_bridge_avalon_slave_slavearbiterlockenable & cpu_data_master_continuerequest;

  //tristate_bridge_avalon_slave_slavearbiterlockenable2 slave enables arbiterlock2, which is an e_assign
  assign tristate_bridge_avalon_slave_slavearbiterlockenable2 = |tristate_bridge_avalon_slave_arb_share_counter_next_value;

  //cpu/data_master tristate_bridge/avalon_slave arbiterlock2, which is an e_assign
  assign cpu_data_master_arbiterlock2 = tristate_bridge_avalon_slave_slavearbiterlockenable2 & cpu_data_master_continuerequest;

  //cpu/instruction_master tristate_bridge/avalon_slave arbiterlock, which is an e_assign
  assign cpu_instruction_master_arbiterlock = tristate_bridge_avalon_slave_slavearbiterlockenable & cpu_instruction_master_continuerequest;

  //cpu/instruction_master tristate_bridge/avalon_slave arbiterlock2, which is an e_assign
  assign cpu_instruction_master_arbiterlock2 = tristate_bridge_avalon_slave_slavearbiterlockenable2 & cpu_instruction_master_continuerequest;

  //cpu/instruction_master granted flash/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_instruction_master_granted_slave_flash_s1 <= 0;
      else if (1)
          last_cycle_cpu_instruction_master_granted_slave_flash_s1 <= cpu_instruction_master_saved_grant_flash_s1 ? 1 : (tristate_bridge_avalon_slave_arbitration_holdoff_internal | ~cpu_instruction_master_requests_flash_s1) ? 0 : last_cycle_cpu_instruction_master_granted_slave_flash_s1;
    end


  //cpu_instruction_master_continuerequest continued request, which is an e_mux
  assign cpu_instruction_master_continuerequest = last_cycle_cpu_instruction_master_granted_slave_flash_s1 & cpu_instruction_master_requests_flash_s1;

  //tristate_bridge_avalon_slave_any_continuerequest at least one master continues requesting, which is an e_mux
  assign tristate_bridge_avalon_slave_any_continuerequest = cpu_instruction_master_continuerequest |
    cpu_data_master_continuerequest;

  assign cpu_data_master_qualified_request_flash_s1 = cpu_data_master_requests_flash_s1 & ~((cpu_data_master_read & (tristate_bridge_avalon_slave_write_pending | (tristate_bridge_avalon_slave_read_pending) | (|cpu_data_master_read_data_valid_flash_s1_shift_register))) | ((~cpu_data_master_waitrequest | tristate_bridge_avalon_slave_read_pending | cpu_data_master_no_byte_enables_and_last_term | !cpu_data_master_byteenable_flash_s1) & cpu_data_master_write) | cpu_instruction_master_arbiterlock);
  //cpu_data_master_read_data_valid_flash_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_data_master_read_data_valid_flash_s1_shift_register_in = cpu_data_master_granted_flash_s1 & cpu_data_master_read & ~flash_s1_waits_for_read & ~(|cpu_data_master_read_data_valid_flash_s1_shift_register);

  //shift register p1 cpu_data_master_read_data_valid_flash_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_data_master_read_data_valid_flash_s1_shift_register = {cpu_data_master_read_data_valid_flash_s1_shift_register, cpu_data_master_read_data_valid_flash_s1_shift_register_in};

  //cpu_data_master_read_data_valid_flash_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_data_master_read_data_valid_flash_s1_shift_register <= 0;
      else if (1)
          cpu_data_master_read_data_valid_flash_s1_shift_register <= p1_cpu_data_master_read_data_valid_flash_s1_shift_register;
    end


  //local readdatavalid cpu_data_master_read_data_valid_flash_s1, which is an e_mux
  assign cpu_data_master_read_data_valid_flash_s1 = cpu_data_master_read_data_valid_flash_s1_shift_register[1];

  //data_to_and_from_the_flash register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          incoming_data_to_and_from_the_flash <= 0;
      else if (1)
          incoming_data_to_and_from_the_flash <= data_to_and_from_the_flash;
    end


  //flash_s1_with_write_latency assignment, which is an e_assign
  assign flash_s1_with_write_latency = in_a_write_cycle & (cpu_data_master_qualified_request_flash_s1 | cpu_instruction_master_qualified_request_flash_s1);

  //time to write the data, which is an e_mux
  assign time_to_write = (flash_s1_with_write_latency)? 1 :
    0;

  //d1_outgoing_data_to_and_from_the_flash register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_outgoing_data_to_and_from_the_flash <= 0;
      else if (1)
          d1_outgoing_data_to_and_from_the_flash <= outgoing_data_to_and_from_the_flash;
    end


  //write cycle delayed by 1, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_in_a_write_cycle <= 0;
      else if (1)
          d1_in_a_write_cycle <= time_to_write;
    end


  //d1_outgoing_data_to_and_from_the_flash tristate driver, which is an e_assign
  assign data_to_and_from_the_flash = (d1_in_a_write_cycle)? d1_outgoing_data_to_and_from_the_flash:{8{1'bz}};

  //outgoing_data_to_and_from_the_flash mux, which is an e_mux
  assign outgoing_data_to_and_from_the_flash = cpu_data_master_dbs_write_8;

  assign cpu_instruction_master_requests_flash_s1 = (({cpu_instruction_master_address_to_slave[23 : 22] , 22'b0} == 24'h800000) & (cpu_instruction_master_read)) & cpu_instruction_master_read;
  //cpu/data_master granted flash/s1 last time, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          last_cycle_cpu_data_master_granted_slave_flash_s1 <= 0;
      else if (1)
          last_cycle_cpu_data_master_granted_slave_flash_s1 <= cpu_data_master_saved_grant_flash_s1 ? 1 : (tristate_bridge_avalon_slave_arbitration_holdoff_internal | ~cpu_data_master_requests_flash_s1) ? 0 : last_cycle_cpu_data_master_granted_slave_flash_s1;
    end


  //cpu_data_master_continuerequest continued request, which is an e_mux
  assign cpu_data_master_continuerequest = last_cycle_cpu_data_master_granted_slave_flash_s1 & cpu_data_master_requests_flash_s1;

  assign cpu_instruction_master_qualified_request_flash_s1 = cpu_instruction_master_requests_flash_s1 & ~((cpu_instruction_master_read & (tristate_bridge_avalon_slave_write_pending | (tristate_bridge_avalon_slave_read_pending) | (2 < cpu_instruction_master_latency_counter))) | cpu_data_master_arbiterlock);
  //cpu_instruction_master_read_data_valid_flash_s1_shift_register_in mux for readlatency shift register, which is an e_mux
  assign cpu_instruction_master_read_data_valid_flash_s1_shift_register_in = cpu_instruction_master_granted_flash_s1 & cpu_instruction_master_read & ~flash_s1_waits_for_read;

  //shift register p1 cpu_instruction_master_read_data_valid_flash_s1_shift_register in if flush, otherwise shift left, which is an e_mux
  assign p1_cpu_instruction_master_read_data_valid_flash_s1_shift_register = {cpu_instruction_master_read_data_valid_flash_s1_shift_register, cpu_instruction_master_read_data_valid_flash_s1_shift_register_in};

  //cpu_instruction_master_read_data_valid_flash_s1_shift_register for remembering which master asked for a fixed latency read, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          cpu_instruction_master_read_data_valid_flash_s1_shift_register <= 0;
      else if (1)
          cpu_instruction_master_read_data_valid_flash_s1_shift_register <= p1_cpu_instruction_master_read_data_valid_flash_s1_shift_register;
    end


  //local readdatavalid cpu_instruction_master_read_data_valid_flash_s1, which is an e_mux
  assign cpu_instruction_master_read_data_valid_flash_s1 = cpu_instruction_master_read_data_valid_flash_s1_shift_register[1];

  //allow new arb cycle for tristate_bridge/avalon_slave, which is an e_assign
  assign tristate_bridge_avalon_slave_allow_new_arb_cycle = ~cpu_data_master_arbiterlock & ~cpu_instruction_master_arbiterlock;

  //cpu/instruction_master assignment into master qualified-requests vector for flash/s1, which is an e_assign
  assign tristate_bridge_avalon_slave_master_qreq_vector[0] = cpu_instruction_master_qualified_request_flash_s1;

  //cpu/instruction_master grant flash/s1, which is an e_assign
  assign cpu_instruction_master_granted_flash_s1 = tristate_bridge_avalon_slave_grant_vector[0];

  //cpu/instruction_master saved-grant flash/s1, which is an e_assign
  assign cpu_instruction_master_saved_grant_flash_s1 = tristate_bridge_avalon_slave_arb_winner[0] && cpu_instruction_master_requests_flash_s1;

  //cpu/data_master assignment into master qualified-requests vector for flash/s1, which is an e_assign
  assign tristate_bridge_avalon_slave_master_qreq_vector[1] = cpu_data_master_qualified_request_flash_s1;

  //cpu/data_master grant flash/s1, which is an e_assign
  assign cpu_data_master_granted_flash_s1 = tristate_bridge_avalon_slave_grant_vector[1];

  //cpu/data_master saved-grant flash/s1, which is an e_assign
  assign cpu_data_master_saved_grant_flash_s1 = tristate_bridge_avalon_slave_arb_winner[1] && cpu_data_master_requests_flash_s1;

  //tristate_bridge/avalon_slave chosen-master double-vector, which is an e_assign
  assign tristate_bridge_avalon_slave_chosen_master_double_vector = {tristate_bridge_avalon_slave_master_qreq_vector, tristate_bridge_avalon_slave_master_qreq_vector} & ({~tristate_bridge_avalon_slave_master_qreq_vector, ~tristate_bridge_avalon_slave_master_qreq_vector} + tristate_bridge_avalon_slave_arb_addend);

  //stable onehot encoding of arb winner
  assign tristate_bridge_avalon_slave_arb_winner = (tristate_bridge_avalon_slave_allow_new_arb_cycle & | tristate_bridge_avalon_slave_grant_vector) ? tristate_bridge_avalon_slave_grant_vector : tristate_bridge_avalon_slave_saved_chosen_master_vector;

  //saved tristate_bridge_avalon_slave_grant_vector, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          tristate_bridge_avalon_slave_saved_chosen_master_vector <= 0;
      else if (tristate_bridge_avalon_slave_allow_new_arb_cycle)
          tristate_bridge_avalon_slave_saved_chosen_master_vector <= |tristate_bridge_avalon_slave_grant_vector ? tristate_bridge_avalon_slave_grant_vector : tristate_bridge_avalon_slave_saved_chosen_master_vector;
    end


  //onehot encoding of chosen master
  assign tristate_bridge_avalon_slave_grant_vector = {(tristate_bridge_avalon_slave_chosen_master_double_vector[1] | tristate_bridge_avalon_slave_chosen_master_double_vector[3]),
    (tristate_bridge_avalon_slave_chosen_master_double_vector[0] | tristate_bridge_avalon_slave_chosen_master_double_vector[2])};

  //tristate_bridge/avalon_slave chosen master rotated left, which is an e_assign
  assign tristate_bridge_avalon_slave_chosen_master_rot_left = (tristate_bridge_avalon_slave_arb_winner << 1) ? (tristate_bridge_avalon_slave_arb_winner << 1) : 1;

  //tristate_bridge/avalon_slave's addend for next-master-grant
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          tristate_bridge_avalon_slave_arb_addend <= 1;
      else if (|tristate_bridge_avalon_slave_grant_vector)
          tristate_bridge_avalon_slave_arb_addend <= tristate_bridge_avalon_slave_end_xfer? tristate_bridge_avalon_slave_chosen_master_rot_left : tristate_bridge_avalon_slave_grant_vector;
    end


  assign p1_select_n_to_the_flash = ~(cpu_data_master_granted_flash_s1 | cpu_instruction_master_granted_flash_s1);
  //tristate_bridge_avalon_slave_firsttransfer first transaction, which is an e_assign
  assign tristate_bridge_avalon_slave_firsttransfer = tristate_bridge_avalon_slave_begins_xfer ? tristate_bridge_avalon_slave_unreg_firsttransfer : tristate_bridge_avalon_slave_reg_firsttransfer;

  //tristate_bridge_avalon_slave_unreg_firsttransfer first transaction, which is an e_assign
  assign tristate_bridge_avalon_slave_unreg_firsttransfer = ~(tristate_bridge_avalon_slave_slavearbiterlockenable & tristate_bridge_avalon_slave_any_continuerequest);

  //tristate_bridge_avalon_slave_reg_firsttransfer first transaction, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          tristate_bridge_avalon_slave_reg_firsttransfer <= 1'b1;
      else if (tristate_bridge_avalon_slave_begins_xfer)
          tristate_bridge_avalon_slave_reg_firsttransfer <= tristate_bridge_avalon_slave_unreg_firsttransfer;
    end


  //tristate_bridge_avalon_slave_beginbursttransfer_internal begin burst transfer, which is an e_assign
  assign tristate_bridge_avalon_slave_beginbursttransfer_internal = tristate_bridge_avalon_slave_begins_xfer;

  //tristate_bridge_avalon_slave_arbitration_holdoff_internal arbitration_holdoff, which is an e_assign
  assign tristate_bridge_avalon_slave_arbitration_holdoff_internal = tristate_bridge_avalon_slave_begins_xfer & tristate_bridge_avalon_slave_firsttransfer;

  //~read_n_to_the_flash of type read to ~p1_read_n_to_the_flash, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          read_n_to_the_flash <= ~0;
      else if (1)
          read_n_to_the_flash <= p1_read_n_to_the_flash;
    end


  //~p1_read_n_to_the_flash assignment, which is an e_mux
  assign p1_read_n_to_the_flash = ~((cpu_data_master_granted_flash_s1 & cpu_data_master_read) | (cpu_instruction_master_granted_flash_s1 & cpu_instruction_master_read));

  //~write_n_to_the_flash of type write to ~p1_write_n_to_the_flash, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          write_n_to_the_flash <= ~0;
      else if (1)
          write_n_to_the_flash <= p1_write_n_to_the_flash;
    end


  //~p1_write_n_to_the_flash assignment, which is an e_mux
  assign p1_write_n_to_the_flash = ~(((cpu_data_master_granted_flash_s1 & cpu_data_master_write)) & flash_s1_pretend_byte_enable);

  //address_to_the_flash of type address to p1_address_to_the_flash, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          address_to_the_flash <= 0;
      else if (1)
          address_to_the_flash <= p1_address_to_the_flash;
    end


  //p1_address_to_the_flash mux, which is an e_mux
  assign p1_address_to_the_flash = (cpu_data_master_granted_flash_s1)? ({cpu_data_master_address_to_slave >> 2,
    cpu_data_master_dbs_address[1 : 0]}) :
    ({cpu_instruction_master_address_to_slave >> 2,
    cpu_instruction_master_dbs_address[1 : 0]});

  //d1_tristate_bridge_avalon_slave_end_xfer register, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          d1_tristate_bridge_avalon_slave_end_xfer <= 1;
      else if (1)
          d1_tristate_bridge_avalon_slave_end_xfer <= tristate_bridge_avalon_slave_end_xfer;
    end


  //flash_s1_waits_for_read in a cycle, which is an e_mux
  assign flash_s1_waits_for_read = flash_s1_in_a_read_cycle & 0;

  //flash_s1_in_a_read_cycle assignment, which is an e_assign
  assign flash_s1_in_a_read_cycle = (cpu_data_master_granted_flash_s1 & cpu_data_master_read) | (cpu_instruction_master_granted_flash_s1 & cpu_instruction_master_read);

  //in_a_read_cycle assignment, which is an e_mux
  assign in_a_read_cycle = flash_s1_in_a_read_cycle;

  //flash_s1_waits_for_write in a cycle, which is an e_mux
  assign flash_s1_waits_for_write = flash_s1_in_a_write_cycle & 0;

  //flash_s1_in_a_write_cycle assignment, which is an e_assign
  assign flash_s1_in_a_write_cycle = cpu_data_master_granted_flash_s1 & cpu_data_master_write;

  //in_a_write_cycle assignment, which is an e_mux
  assign in_a_write_cycle = flash_s1_in_a_write_cycle;

  assign wait_for_flash_s1_counter = 0;
  //flash_s1_pretend_byte_enable byte enable port mux, which is an e_mux
  assign flash_s1_pretend_byte_enable = (cpu_data_master_granted_flash_s1)? cpu_data_master_byteenable_flash_s1 :
    -1;

  assign {cpu_data_master_byteenable_flash_s1_segment_3,
cpu_data_master_byteenable_flash_s1_segment_2,
cpu_data_master_byteenable_flash_s1_segment_1,
cpu_data_master_byteenable_flash_s1_segment_0} = cpu_data_master_byteenable;
  assign cpu_data_master_byteenable_flash_s1 = ((cpu_data_master_dbs_address[1 : 0] == 0))? cpu_data_master_byteenable_flash_s1_segment_0 :
    ((cpu_data_master_dbs_address[1 : 0] == 1))? cpu_data_master_byteenable_flash_s1_segment_1 :
    ((cpu_data_master_dbs_address[1 : 0] == 2))? cpu_data_master_byteenable_flash_s1_segment_2 :
    cpu_data_master_byteenable_flash_s1_segment_3;


//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  //incoming_data_to_and_from_the_flash_bit_0_is_x x check, which is an e_assign_is_x
  assign incoming_data_to_and_from_the_flash_bit_0_is_x = ^(incoming_data_to_and_from_the_flash[0]) === 1'bx;

  //Crush incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[0] Xs to 0, which is an e_assign
  assign incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[0] = incoming_data_to_and_from_the_flash_bit_0_is_x ? 1'b0 : incoming_data_to_and_from_the_flash[0];

  //incoming_data_to_and_from_the_flash_bit_1_is_x x check, which is an e_assign_is_x
  assign incoming_data_to_and_from_the_flash_bit_1_is_x = ^(incoming_data_to_and_from_the_flash[1]) === 1'bx;

  //Crush incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[1] Xs to 0, which is an e_assign
  assign incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[1] = incoming_data_to_and_from_the_flash_bit_1_is_x ? 1'b0 : incoming_data_to_and_from_the_flash[1];

  //incoming_data_to_and_from_the_flash_bit_2_is_x x check, which is an e_assign_is_x
  assign incoming_data_to_and_from_the_flash_bit_2_is_x = ^(incoming_data_to_and_from_the_flash[2]) === 1'bx;

  //Crush incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[2] Xs to 0, which is an e_assign
  assign incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[2] = incoming_data_to_and_from_the_flash_bit_2_is_x ? 1'b0 : incoming_data_to_and_from_the_flash[2];

  //incoming_data_to_and_from_the_flash_bit_3_is_x x check, which is an e_assign_is_x
  assign incoming_data_to_and_from_the_flash_bit_3_is_x = ^(incoming_data_to_and_from_the_flash[3]) === 1'bx;

  //Crush incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[3] Xs to 0, which is an e_assign
  assign incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[3] = incoming_data_to_and_from_the_flash_bit_3_is_x ? 1'b0 : incoming_data_to_and_from_the_flash[3];

  //incoming_data_to_and_from_the_flash_bit_4_is_x x check, which is an e_assign_is_x
  assign incoming_data_to_and_from_the_flash_bit_4_is_x = ^(incoming_data_to_and_from_the_flash[4]) === 1'bx;

  //Crush incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[4] Xs to 0, which is an e_assign
  assign incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[4] = incoming_data_to_and_from_the_flash_bit_4_is_x ? 1'b0 : incoming_data_to_and_from_the_flash[4];

  //incoming_data_to_and_from_the_flash_bit_5_is_x x check, which is an e_assign_is_x
  assign incoming_data_to_and_from_the_flash_bit_5_is_x = ^(incoming_data_to_and_from_the_flash[5]) === 1'bx;

  //Crush incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[5] Xs to 0, which is an e_assign
  assign incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[5] = incoming_data_to_and_from_the_flash_bit_5_is_x ? 1'b0 : incoming_data_to_and_from_the_flash[5];

  //incoming_data_to_and_from_the_flash_bit_6_is_x x check, which is an e_assign_is_x
  assign incoming_data_to_and_from_the_flash_bit_6_is_x = ^(incoming_data_to_and_from_the_flash[6]) === 1'bx;

  //Crush incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[6] Xs to 0, which is an e_assign
  assign incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[6] = incoming_data_to_and_from_the_flash_bit_6_is_x ? 1'b0 : incoming_data_to_and_from_the_flash[6];

  //incoming_data_to_and_from_the_flash_bit_7_is_x x check, which is an e_assign_is_x
  assign incoming_data_to_and_from_the_flash_bit_7_is_x = ^(incoming_data_to_and_from_the_flash[7]) === 1'bx;

  //Crush incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[7] Xs to 0, which is an e_assign
  assign incoming_data_to_and_from_the_flash_with_Xs_converted_to_0[7] = incoming_data_to_and_from_the_flash_bit_7_is_x ? 1'b0 : incoming_data_to_and_from_the_flash[7];

  //flash/s1 enable non-zero assertions, which is an e_register
  always @(posedge clk or negedge reset_n)
    begin
      if (reset_n == 0)
          enable_nonzero_assertions <= 0;
      else if (1)
          enable_nonzero_assertions <= 1'b1;
    end


  //grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_granted_flash_s1 + cpu_instruction_master_granted_flash_s1 > 1)
        begin
          $write("%0d ns: > 1 of grant signals are active simultaneously", $time);
          $stop;
        end
    end


  //saved_grant signals are active simultaneously, which is an e_process
  always @(posedge clk)
    begin
      if (cpu_data_master_saved_grant_flash_s1 + cpu_instruction_master_saved_grant_flash_s1 > 1)
        begin
          $write("%0d ns: > 1 of saved_grant signals are active simultaneously", $time);
          $stop;
        end
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  
//  assign incoming_data_to_and_from_the_flash_with_Xs_converted_to_0 = incoming_data_to_and_from_the_flash;
//
//synthesis read_comments_as_HDL off

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module tristate_bridge_bridge_arbitrator 
;



endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module testPro (
                 // 1) global signals:
                  clk,
                  reset_n,

                 // the_Din
                  in_port_to_the_Din,

                 // the_Dout
                  out_port_from_the_Dout,

                 // the_SEG_H
                  out_port_from_the_SEG_H,

                 // the_SEG_l
                  out_port_from_the_SEG_l,

                 // the_addr
                  out_port_from_the_addr,

                 // the_character_lcd_0
                  LCD_BLON_from_the_character_lcd_0,
                  LCD_DATA_to_and_from_the_character_lcd_0,
                  LCD_EN_from_the_character_lcd_0,
                  LCD_ON_from_the_character_lcd_0,
                  LCD_RS_from_the_character_lcd_0,
                  LCD_RW_from_the_character_lcd_0,

                 // the_nCS
                  out_port_from_the_nCS,

                 // the_nRD
                  out_port_from_the_nRD,

                 // the_nWR
                  out_port_from_the_nWR,

                 // the_ps2_0
                  PS2_CLK_to_and_from_the_ps2_0,
                  PS2_DAT_to_and_from_the_ps2_0,

                 // the_sram_0
                  SRAM_ADDR_from_the_sram_0,
                  SRAM_CE_N_from_the_sram_0,
                  SRAM_DQ_to_and_from_the_sram_0,
                  SRAM_LB_N_from_the_sram_0,
                  SRAM_OE_N_from_the_sram_0,
                  SRAM_UB_N_from_the_sram_0,
                  SRAM_WE_N_from_the_sram_0,

                 // the_tristate_bridge_avalon_slave
                  address_to_the_flash,
                  data_to_and_from_the_flash,
                  read_n_to_the_flash,
                  select_n_to_the_flash,
                  write_n_to_the_flash
               )
;

  output           LCD_BLON_from_the_character_lcd_0;
  inout   [  7: 0] LCD_DATA_to_and_from_the_character_lcd_0;
  output           LCD_EN_from_the_character_lcd_0;
  output           LCD_ON_from_the_character_lcd_0;
  output           LCD_RS_from_the_character_lcd_0;
  output           LCD_RW_from_the_character_lcd_0;
  inout            PS2_CLK_to_and_from_the_ps2_0;
  inout            PS2_DAT_to_and_from_the_ps2_0;
  output  [ 17: 0] SRAM_ADDR_from_the_sram_0;
  output           SRAM_CE_N_from_the_sram_0;
  inout   [ 15: 0] SRAM_DQ_to_and_from_the_sram_0;
  output           SRAM_LB_N_from_the_sram_0;
  output           SRAM_OE_N_from_the_sram_0;
  output           SRAM_UB_N_from_the_sram_0;
  output           SRAM_WE_N_from_the_sram_0;
  output  [ 21: 0] address_to_the_flash;
  inout   [  7: 0] data_to_and_from_the_flash;
  output  [  7: 0] out_port_from_the_Dout;
  output  [  7: 0] out_port_from_the_SEG_H;
  output  [  7: 0] out_port_from_the_SEG_l;
  output  [  1: 0] out_port_from_the_addr;
  output           out_port_from_the_nCS;
  output           out_port_from_the_nRD;
  output           out_port_from_the_nWR;
  output           read_n_to_the_flash;
  output           select_n_to_the_flash;
  output           write_n_to_the_flash;
  input            clk;
  input   [  7: 0] in_port_to_the_Din;
  input            reset_n;

  wire    [  1: 0] Din_s1_address;
  wire    [  7: 0] Din_s1_readdata;
  wire    [  7: 0] Din_s1_readdata_from_sa;
  wire             Din_s1_reset_n;
  wire    [  1: 0] Dout_s1_address;
  wire             Dout_s1_chipselect;
  wire             Dout_s1_reset_n;
  wire             Dout_s1_write_n;
  wire    [  7: 0] Dout_s1_writedata;
  wire             LCD_BLON_from_the_character_lcd_0;
  wire    [  7: 0] LCD_DATA_to_and_from_the_character_lcd_0;
  wire             LCD_EN_from_the_character_lcd_0;
  wire             LCD_ON_from_the_character_lcd_0;
  wire             LCD_RS_from_the_character_lcd_0;
  wire             LCD_RW_from_the_character_lcd_0;
  wire             PS2_CLK_to_and_from_the_ps2_0;
  wire             PS2_DAT_to_and_from_the_ps2_0;
  wire    [  1: 0] SEG_H_s1_address;
  wire             SEG_H_s1_chipselect;
  wire             SEG_H_s1_reset_n;
  wire             SEG_H_s1_write_n;
  wire    [  7: 0] SEG_H_s1_writedata;
  wire    [  1: 0] SEG_l_s1_address;
  wire             SEG_l_s1_chipselect;
  wire             SEG_l_s1_reset_n;
  wire             SEG_l_s1_write_n;
  wire    [  7: 0] SEG_l_s1_writedata;
  wire    [ 17: 0] SRAM_ADDR_from_the_sram_0;
  wire             SRAM_CE_N_from_the_sram_0;
  wire    [ 15: 0] SRAM_DQ_to_and_from_the_sram_0;
  wire             SRAM_LB_N_from_the_sram_0;
  wire             SRAM_OE_N_from_the_sram_0;
  wire             SRAM_UB_N_from_the_sram_0;
  wire             SRAM_WE_N_from_the_sram_0;
  wire    [  1: 0] addr_s1_address;
  wire             addr_s1_chipselect;
  wire             addr_s1_reset_n;
  wire             addr_s1_write_n;
  wire    [  1: 0] addr_s1_writedata;
  wire    [ 21: 0] address_to_the_flash;
  wire             character_lcd_0_avalon_lcd_slave_address;
  wire             character_lcd_0_avalon_lcd_slave_chipselect;
  wire             character_lcd_0_avalon_lcd_slave_read;
  wire    [ 31: 0] character_lcd_0_avalon_lcd_slave_readdata;
  wire    [ 31: 0] character_lcd_0_avalon_lcd_slave_readdata_from_sa;
  wire             character_lcd_0_avalon_lcd_slave_waitrequest;
  wire             character_lcd_0_avalon_lcd_slave_waitrequest_from_sa;
  wire             character_lcd_0_avalon_lcd_slave_write;
  wire    [ 31: 0] character_lcd_0_avalon_lcd_slave_writedata;
  wire             clk_reset;
  wire             clk_reset_n;
  wire    [ 23: 0] cpu_data_master_address;
  wire    [ 23: 0] cpu_data_master_address_to_slave;
  wire    [  3: 0] cpu_data_master_byteenable;
  wire             cpu_data_master_byteenable_flash_s1;
  wire    [  1: 0] cpu_data_master_byteenable_sram_0_avalon_sram_slave;
  wire    [  1: 0] cpu_data_master_dbs_address;
  wire    [ 15: 0] cpu_data_master_dbs_write_16;
  wire    [  7: 0] cpu_data_master_dbs_write_8;
  wire             cpu_data_master_debugaccess;
  wire             cpu_data_master_granted_Din_s1;
  wire             cpu_data_master_granted_Dout_s1;
  wire             cpu_data_master_granted_SEG_H_s1;
  wire             cpu_data_master_granted_SEG_l_s1;
  wire             cpu_data_master_granted_addr_s1;
  wire             cpu_data_master_granted_character_lcd_0_avalon_lcd_slave;
  wire             cpu_data_master_granted_cpu_jtag_debug_module;
  wire             cpu_data_master_granted_flash_s1;
  wire             cpu_data_master_granted_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_granted_nCS_s1;
  wire             cpu_data_master_granted_nRD_s1;
  wire             cpu_data_master_granted_nWR_s1;
  wire             cpu_data_master_granted_ps2_0_avalon_PS2_slave;
  wire             cpu_data_master_granted_sram_0_avalon_sram_slave;
  wire             cpu_data_master_granted_sysid_control_slave;
  wire             cpu_data_master_granted_timer_s1;
  wire    [ 31: 0] cpu_data_master_irq;
  wire             cpu_data_master_no_byte_enables_and_last_term;
  wire             cpu_data_master_qualified_request_Din_s1;
  wire             cpu_data_master_qualified_request_Dout_s1;
  wire             cpu_data_master_qualified_request_SEG_H_s1;
  wire             cpu_data_master_qualified_request_SEG_l_s1;
  wire             cpu_data_master_qualified_request_addr_s1;
  wire             cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave;
  wire             cpu_data_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_data_master_qualified_request_flash_s1;
  wire             cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_qualified_request_nCS_s1;
  wire             cpu_data_master_qualified_request_nRD_s1;
  wire             cpu_data_master_qualified_request_nWR_s1;
  wire             cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave;
  wire             cpu_data_master_qualified_request_sram_0_avalon_sram_slave;
  wire             cpu_data_master_qualified_request_sysid_control_slave;
  wire             cpu_data_master_qualified_request_timer_s1;
  wire             cpu_data_master_read;
  wire             cpu_data_master_read_data_valid_Din_s1;
  wire             cpu_data_master_read_data_valid_Dout_s1;
  wire             cpu_data_master_read_data_valid_SEG_H_s1;
  wire             cpu_data_master_read_data_valid_SEG_l_s1;
  wire             cpu_data_master_read_data_valid_addr_s1;
  wire             cpu_data_master_read_data_valid_character_lcd_0_avalon_lcd_slave;
  wire             cpu_data_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_data_master_read_data_valid_flash_s1;
  wire             cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_read_data_valid_nCS_s1;
  wire             cpu_data_master_read_data_valid_nRD_s1;
  wire             cpu_data_master_read_data_valid_nWR_s1;
  wire             cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave;
  wire             cpu_data_master_read_data_valid_sram_0_avalon_sram_slave;
  wire             cpu_data_master_read_data_valid_sysid_control_slave;
  wire             cpu_data_master_read_data_valid_timer_s1;
  wire    [ 31: 0] cpu_data_master_readdata;
  wire             cpu_data_master_requests_Din_s1;
  wire             cpu_data_master_requests_Dout_s1;
  wire             cpu_data_master_requests_SEG_H_s1;
  wire             cpu_data_master_requests_SEG_l_s1;
  wire             cpu_data_master_requests_addr_s1;
  wire             cpu_data_master_requests_character_lcd_0_avalon_lcd_slave;
  wire             cpu_data_master_requests_cpu_jtag_debug_module;
  wire             cpu_data_master_requests_flash_s1;
  wire             cpu_data_master_requests_jtag_uart_avalon_jtag_slave;
  wire             cpu_data_master_requests_nCS_s1;
  wire             cpu_data_master_requests_nRD_s1;
  wire             cpu_data_master_requests_nWR_s1;
  wire             cpu_data_master_requests_ps2_0_avalon_PS2_slave;
  wire             cpu_data_master_requests_sram_0_avalon_sram_slave;
  wire             cpu_data_master_requests_sysid_control_slave;
  wire             cpu_data_master_requests_timer_s1;
  wire             cpu_data_master_waitrequest;
  wire             cpu_data_master_write;
  wire    [ 31: 0] cpu_data_master_writedata;
  wire    [ 23: 0] cpu_instruction_master_address;
  wire    [ 23: 0] cpu_instruction_master_address_to_slave;
  wire    [  1: 0] cpu_instruction_master_dbs_address;
  wire             cpu_instruction_master_granted_cpu_jtag_debug_module;
  wire             cpu_instruction_master_granted_flash_s1;
  wire             cpu_instruction_master_granted_sram_0_avalon_sram_slave;
  wire    [  1: 0] cpu_instruction_master_latency_counter;
  wire             cpu_instruction_master_qualified_request_cpu_jtag_debug_module;
  wire             cpu_instruction_master_qualified_request_flash_s1;
  wire             cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave;
  wire             cpu_instruction_master_read;
  wire             cpu_instruction_master_read_data_valid_cpu_jtag_debug_module;
  wire             cpu_instruction_master_read_data_valid_flash_s1;
  wire             cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave;
  wire    [ 31: 0] cpu_instruction_master_readdata;
  wire             cpu_instruction_master_readdatavalid;
  wire             cpu_instruction_master_requests_cpu_jtag_debug_module;
  wire             cpu_instruction_master_requests_flash_s1;
  wire             cpu_instruction_master_requests_sram_0_avalon_sram_slave;
  wire             cpu_instruction_master_waitrequest;
  wire    [  8: 0] cpu_jtag_debug_module_address;
  wire             cpu_jtag_debug_module_begintransfer;
  wire    [  3: 0] cpu_jtag_debug_module_byteenable;
  wire             cpu_jtag_debug_module_chipselect;
  wire             cpu_jtag_debug_module_debugaccess;
  wire    [ 31: 0] cpu_jtag_debug_module_readdata;
  wire    [ 31: 0] cpu_jtag_debug_module_readdata_from_sa;
  wire             cpu_jtag_debug_module_reset;
  wire             cpu_jtag_debug_module_reset_n;
  wire             cpu_jtag_debug_module_resetrequest;
  wire             cpu_jtag_debug_module_resetrequest_from_sa;
  wire             cpu_jtag_debug_module_write;
  wire    [ 31: 0] cpu_jtag_debug_module_writedata;
  wire             d1_Din_s1_end_xfer;
  wire             d1_Dout_s1_end_xfer;
  wire             d1_SEG_H_s1_end_xfer;
  wire             d1_SEG_l_s1_end_xfer;
  wire             d1_addr_s1_end_xfer;
  wire             d1_character_lcd_0_avalon_lcd_slave_end_xfer;
  wire             d1_cpu_jtag_debug_module_end_xfer;
  wire             d1_jtag_uart_avalon_jtag_slave_end_xfer;
  wire             d1_nCS_s1_end_xfer;
  wire             d1_nRD_s1_end_xfer;
  wire             d1_nWR_s1_end_xfer;
  wire             d1_ps2_0_avalon_PS2_slave_end_xfer;
  wire             d1_sram_0_avalon_sram_slave_end_xfer;
  wire             d1_sysid_control_slave_end_xfer;
  wire             d1_timer_s1_end_xfer;
  wire             d1_tristate_bridge_avalon_slave_end_xfer;
  wire    [  7: 0] data_to_and_from_the_flash;
  wire    [  7: 0] incoming_data_to_and_from_the_flash;
  wire    [  7: 0] incoming_data_to_and_from_the_flash_with_Xs_converted_to_0;
  wire             jtag_uart_avalon_jtag_slave_address;
  wire             jtag_uart_avalon_jtag_slave_chipselect;
  wire             jtag_uart_avalon_jtag_slave_dataavailable;
  wire             jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_avalon_jtag_slave_irq;
  wire             jtag_uart_avalon_jtag_slave_irq_from_sa;
  wire             jtag_uart_avalon_jtag_slave_read_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_readdata;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_readdata_from_sa;
  wire             jtag_uart_avalon_jtag_slave_readyfordata;
  wire             jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  wire             jtag_uart_avalon_jtag_slave_reset_n;
  wire             jtag_uart_avalon_jtag_slave_waitrequest;
  wire             jtag_uart_avalon_jtag_slave_waitrequest_from_sa;
  wire             jtag_uart_avalon_jtag_slave_write_n;
  wire    [ 31: 0] jtag_uart_avalon_jtag_slave_writedata;
  wire    [  1: 0] nCS_s1_address;
  wire             nCS_s1_chipselect;
  wire             nCS_s1_reset_n;
  wire             nCS_s1_write_n;
  wire             nCS_s1_writedata;
  wire    [  1: 0] nRD_s1_address;
  wire             nRD_s1_chipselect;
  wire             nRD_s1_reset_n;
  wire             nRD_s1_write_n;
  wire             nRD_s1_writedata;
  wire    [  1: 0] nWR_s1_address;
  wire             nWR_s1_chipselect;
  wire             nWR_s1_reset_n;
  wire             nWR_s1_write_n;
  wire             nWR_s1_writedata;
  wire    [  7: 0] out_port_from_the_Dout;
  wire    [  7: 0] out_port_from_the_SEG_H;
  wire    [  7: 0] out_port_from_the_SEG_l;
  wire    [  1: 0] out_port_from_the_addr;
  wire             out_port_from_the_nCS;
  wire             out_port_from_the_nRD;
  wire             out_port_from_the_nWR;
  wire             ps2_0_avalon_PS2_slave_address;
  wire    [  3: 0] ps2_0_avalon_PS2_slave_byteenable;
  wire             ps2_0_avalon_PS2_slave_chipselect;
  wire             ps2_0_avalon_PS2_slave_irq;
  wire             ps2_0_avalon_PS2_slave_irq_from_sa;
  wire             ps2_0_avalon_PS2_slave_read;
  wire    [ 31: 0] ps2_0_avalon_PS2_slave_readdata;
  wire    [ 31: 0] ps2_0_avalon_PS2_slave_readdata_from_sa;
  wire             ps2_0_avalon_PS2_slave_waitrequest;
  wire             ps2_0_avalon_PS2_slave_waitrequest_from_sa;
  wire             ps2_0_avalon_PS2_slave_write;
  wire    [ 31: 0] ps2_0_avalon_PS2_slave_writedata;
  wire             read_n_to_the_flash;
  wire             registered_cpu_data_master_read_data_valid_flash_s1;
  wire             registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave;
  wire             registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave;
  wire             reset_n_sources;
  wire             select_n_to_the_flash;
  wire    [ 17: 0] sram_0_avalon_sram_slave_address;
  wire    [  1: 0] sram_0_avalon_sram_slave_byteenable;
  wire             sram_0_avalon_sram_slave_chipselect;
  wire             sram_0_avalon_sram_slave_read;
  wire    [ 15: 0] sram_0_avalon_sram_slave_readdata;
  wire    [ 15: 0] sram_0_avalon_sram_slave_readdata_from_sa;
  wire             sram_0_avalon_sram_slave_write;
  wire    [ 15: 0] sram_0_avalon_sram_slave_writedata;
  wire             sysid_control_slave_address;
  wire    [ 31: 0] sysid_control_slave_readdata;
  wire    [ 31: 0] sysid_control_slave_readdata_from_sa;
  wire    [  2: 0] timer_s1_address;
  wire             timer_s1_chipselect;
  wire             timer_s1_irq;
  wire             timer_s1_irq_from_sa;
  wire    [ 15: 0] timer_s1_readdata;
  wire    [ 15: 0] timer_s1_readdata_from_sa;
  wire             timer_s1_reset_n;
  wire             timer_s1_write_n;
  wire    [ 15: 0] timer_s1_writedata;
  wire             write_n_to_the_flash;
  Din_s1_arbitrator the_Din_s1
    (
      .Din_s1_address                           (Din_s1_address),
      .Din_s1_readdata                          (Din_s1_readdata),
      .Din_s1_readdata_from_sa                  (Din_s1_readdata_from_sa),
      .Din_s1_reset_n                           (Din_s1_reset_n),
      .clk                                      (clk),
      .cpu_data_master_address_to_slave         (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_Din_s1           (cpu_data_master_granted_Din_s1),
      .cpu_data_master_qualified_request_Din_s1 (cpu_data_master_qualified_request_Din_s1),
      .cpu_data_master_read                     (cpu_data_master_read),
      .cpu_data_master_read_data_valid_Din_s1   (cpu_data_master_read_data_valid_Din_s1),
      .cpu_data_master_requests_Din_s1          (cpu_data_master_requests_Din_s1),
      .cpu_data_master_write                    (cpu_data_master_write),
      .d1_Din_s1_end_xfer                       (d1_Din_s1_end_xfer),
      .reset_n                                  (clk_reset_n)
    );

  Din the_Din
    (
      .address  (Din_s1_address),
      .clk      (clk),
      .in_port  (in_port_to_the_Din),
      .readdata (Din_s1_readdata),
      .reset_n  (Din_s1_reset_n)
    );

  Dout_s1_arbitrator the_Dout_s1
    (
      .Dout_s1_address                           (Dout_s1_address),
      .Dout_s1_chipselect                        (Dout_s1_chipselect),
      .Dout_s1_reset_n                           (Dout_s1_reset_n),
      .Dout_s1_write_n                           (Dout_s1_write_n),
      .Dout_s1_writedata                         (Dout_s1_writedata),
      .clk                                       (clk),
      .cpu_data_master_address_to_slave          (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                (cpu_data_master_byteenable),
      .cpu_data_master_granted_Dout_s1           (cpu_data_master_granted_Dout_s1),
      .cpu_data_master_qualified_request_Dout_s1 (cpu_data_master_qualified_request_Dout_s1),
      .cpu_data_master_read                      (cpu_data_master_read),
      .cpu_data_master_read_data_valid_Dout_s1   (cpu_data_master_read_data_valid_Dout_s1),
      .cpu_data_master_requests_Dout_s1          (cpu_data_master_requests_Dout_s1),
      .cpu_data_master_waitrequest               (cpu_data_master_waitrequest),
      .cpu_data_master_write                     (cpu_data_master_write),
      .cpu_data_master_writedata                 (cpu_data_master_writedata),
      .d1_Dout_s1_end_xfer                       (d1_Dout_s1_end_xfer),
      .reset_n                                   (clk_reset_n)
    );

  Dout the_Dout
    (
      .address    (Dout_s1_address),
      .chipselect (Dout_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_Dout),
      .reset_n    (Dout_s1_reset_n),
      .write_n    (Dout_s1_write_n),
      .writedata  (Dout_s1_writedata)
    );

  SEG_H_s1_arbitrator the_SEG_H_s1
    (
      .SEG_H_s1_address                           (SEG_H_s1_address),
      .SEG_H_s1_chipselect                        (SEG_H_s1_chipselect),
      .SEG_H_s1_reset_n                           (SEG_H_s1_reset_n),
      .SEG_H_s1_write_n                           (SEG_H_s1_write_n),
      .SEG_H_s1_writedata                         (SEG_H_s1_writedata),
      .clk                                        (clk),
      .cpu_data_master_address_to_slave           (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                 (cpu_data_master_byteenable),
      .cpu_data_master_granted_SEG_H_s1           (cpu_data_master_granted_SEG_H_s1),
      .cpu_data_master_qualified_request_SEG_H_s1 (cpu_data_master_qualified_request_SEG_H_s1),
      .cpu_data_master_read                       (cpu_data_master_read),
      .cpu_data_master_read_data_valid_SEG_H_s1   (cpu_data_master_read_data_valid_SEG_H_s1),
      .cpu_data_master_requests_SEG_H_s1          (cpu_data_master_requests_SEG_H_s1),
      .cpu_data_master_waitrequest                (cpu_data_master_waitrequest),
      .cpu_data_master_write                      (cpu_data_master_write),
      .cpu_data_master_writedata                  (cpu_data_master_writedata),
      .d1_SEG_H_s1_end_xfer                       (d1_SEG_H_s1_end_xfer),
      .reset_n                                    (clk_reset_n)
    );

  SEG_H the_SEG_H
    (
      .address    (SEG_H_s1_address),
      .chipselect (SEG_H_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_SEG_H),
      .reset_n    (SEG_H_s1_reset_n),
      .write_n    (SEG_H_s1_write_n),
      .writedata  (SEG_H_s1_writedata)
    );

  SEG_l_s1_arbitrator the_SEG_l_s1
    (
      .SEG_l_s1_address                           (SEG_l_s1_address),
      .SEG_l_s1_chipselect                        (SEG_l_s1_chipselect),
      .SEG_l_s1_reset_n                           (SEG_l_s1_reset_n),
      .SEG_l_s1_write_n                           (SEG_l_s1_write_n),
      .SEG_l_s1_writedata                         (SEG_l_s1_writedata),
      .clk                                        (clk),
      .cpu_data_master_address_to_slave           (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                 (cpu_data_master_byteenable),
      .cpu_data_master_granted_SEG_l_s1           (cpu_data_master_granted_SEG_l_s1),
      .cpu_data_master_qualified_request_SEG_l_s1 (cpu_data_master_qualified_request_SEG_l_s1),
      .cpu_data_master_read                       (cpu_data_master_read),
      .cpu_data_master_read_data_valid_SEG_l_s1   (cpu_data_master_read_data_valid_SEG_l_s1),
      .cpu_data_master_requests_SEG_l_s1          (cpu_data_master_requests_SEG_l_s1),
      .cpu_data_master_waitrequest                (cpu_data_master_waitrequest),
      .cpu_data_master_write                      (cpu_data_master_write),
      .cpu_data_master_writedata                  (cpu_data_master_writedata),
      .d1_SEG_l_s1_end_xfer                       (d1_SEG_l_s1_end_xfer),
      .reset_n                                    (clk_reset_n)
    );

  SEG_l the_SEG_l
    (
      .address    (SEG_l_s1_address),
      .chipselect (SEG_l_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_SEG_l),
      .reset_n    (SEG_l_s1_reset_n),
      .write_n    (SEG_l_s1_write_n),
      .writedata  (SEG_l_s1_writedata)
    );

  addr_s1_arbitrator the_addr_s1
    (
      .addr_s1_address                           (addr_s1_address),
      .addr_s1_chipselect                        (addr_s1_chipselect),
      .addr_s1_reset_n                           (addr_s1_reset_n),
      .addr_s1_write_n                           (addr_s1_write_n),
      .addr_s1_writedata                         (addr_s1_writedata),
      .clk                                       (clk),
      .cpu_data_master_address_to_slave          (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_addr_s1           (cpu_data_master_granted_addr_s1),
      .cpu_data_master_qualified_request_addr_s1 (cpu_data_master_qualified_request_addr_s1),
      .cpu_data_master_read                      (cpu_data_master_read),
      .cpu_data_master_read_data_valid_addr_s1   (cpu_data_master_read_data_valid_addr_s1),
      .cpu_data_master_requests_addr_s1          (cpu_data_master_requests_addr_s1),
      .cpu_data_master_waitrequest               (cpu_data_master_waitrequest),
      .cpu_data_master_write                     (cpu_data_master_write),
      .cpu_data_master_writedata                 (cpu_data_master_writedata),
      .d1_addr_s1_end_xfer                       (d1_addr_s1_end_xfer),
      .reset_n                                   (clk_reset_n)
    );

  addr the_addr
    (
      .address    (addr_s1_address),
      .chipselect (addr_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_addr),
      .reset_n    (addr_s1_reset_n),
      .write_n    (addr_s1_write_n),
      .writedata  (addr_s1_writedata)
    );

  character_lcd_0_avalon_lcd_slave_arbitrator the_character_lcd_0_avalon_lcd_slave
    (
      .character_lcd_0_avalon_lcd_slave_address                           (character_lcd_0_avalon_lcd_slave_address),
      .character_lcd_0_avalon_lcd_slave_chipselect                        (character_lcd_0_avalon_lcd_slave_chipselect),
      .character_lcd_0_avalon_lcd_slave_read                              (character_lcd_0_avalon_lcd_slave_read),
      .character_lcd_0_avalon_lcd_slave_readdata                          (character_lcd_0_avalon_lcd_slave_readdata),
      .character_lcd_0_avalon_lcd_slave_readdata_from_sa                  (character_lcd_0_avalon_lcd_slave_readdata_from_sa),
      .character_lcd_0_avalon_lcd_slave_waitrequest                       (character_lcd_0_avalon_lcd_slave_waitrequest),
      .character_lcd_0_avalon_lcd_slave_waitrequest_from_sa               (character_lcd_0_avalon_lcd_slave_waitrequest_from_sa),
      .character_lcd_0_avalon_lcd_slave_write                             (character_lcd_0_avalon_lcd_slave_write),
      .character_lcd_0_avalon_lcd_slave_writedata                         (character_lcd_0_avalon_lcd_slave_writedata),
      .clk                                                                (clk),
      .cpu_data_master_address_to_slave                                   (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_character_lcd_0_avalon_lcd_slave           (cpu_data_master_granted_character_lcd_0_avalon_lcd_slave),
      .cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave (cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave),
      .cpu_data_master_read                                               (cpu_data_master_read),
      .cpu_data_master_read_data_valid_character_lcd_0_avalon_lcd_slave   (cpu_data_master_read_data_valid_character_lcd_0_avalon_lcd_slave),
      .cpu_data_master_requests_character_lcd_0_avalon_lcd_slave          (cpu_data_master_requests_character_lcd_0_avalon_lcd_slave),
      .cpu_data_master_waitrequest                                        (cpu_data_master_waitrequest),
      .cpu_data_master_write                                              (cpu_data_master_write),
      .cpu_data_master_writedata                                          (cpu_data_master_writedata),
      .d1_character_lcd_0_avalon_lcd_slave_end_xfer                       (d1_character_lcd_0_avalon_lcd_slave_end_xfer),
      .reset_n                                                            (clk_reset_n)
    );

  //complemented clk_reset_n, which is an e_assign
  assign clk_reset = ~clk_reset_n;

  //reset is asserted asynchronously and deasserted synchronously
  testPro_reset_clk_domain_synch_module testPro_reset_clk_domain_synch
    (
      .clk      (clk),
      .data_in  (1'b1),
      .data_out (clk_reset_n),
      .reset_n  (reset_n_sources)
    );

  //reset sources mux, which is an e_mux
  assign reset_n_sources = ~(~reset_n |
    0 |
    cpu_jtag_debug_module_resetrequest_from_sa |
    cpu_jtag_debug_module_resetrequest_from_sa);

  character_lcd_0 the_character_lcd_0
    (
      .LCD_BLON    (LCD_BLON_from_the_character_lcd_0),
      .LCD_DATA    (LCD_DATA_to_and_from_the_character_lcd_0),
      .LCD_EN      (LCD_EN_from_the_character_lcd_0),
      .LCD_ON      (LCD_ON_from_the_character_lcd_0),
      .LCD_RS      (LCD_RS_from_the_character_lcd_0),
      .LCD_RW      (LCD_RW_from_the_character_lcd_0),
      .address     (character_lcd_0_avalon_lcd_slave_address),
      .chipselect  (character_lcd_0_avalon_lcd_slave_chipselect),
      .clk         (clk),
      .read        (character_lcd_0_avalon_lcd_slave_read),
      .readdata    (character_lcd_0_avalon_lcd_slave_readdata),
      .reset       (clk_reset),
      .waitrequest (character_lcd_0_avalon_lcd_slave_waitrequest),
      .write       (character_lcd_0_avalon_lcd_slave_write),
      .writedata   (character_lcd_0_avalon_lcd_slave_writedata)
    );

  cpu_jtag_debug_module_arbitrator the_cpu_jtag_debug_module
    (
      .clk                                                            (clk),
      .cpu_data_master_address_to_slave                               (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                                     (cpu_data_master_byteenable),
      .cpu_data_master_debugaccess                                    (cpu_data_master_debugaccess),
      .cpu_data_master_granted_cpu_jtag_debug_module                  (cpu_data_master_granted_cpu_jtag_debug_module),
      .cpu_data_master_qualified_request_cpu_jtag_debug_module        (cpu_data_master_qualified_request_cpu_jtag_debug_module),
      .cpu_data_master_read                                           (cpu_data_master_read),
      .cpu_data_master_read_data_valid_cpu_jtag_debug_module          (cpu_data_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_data_master_requests_cpu_jtag_debug_module                 (cpu_data_master_requests_cpu_jtag_debug_module),
      .cpu_data_master_waitrequest                                    (cpu_data_master_waitrequest),
      .cpu_data_master_write                                          (cpu_data_master_write),
      .cpu_data_master_writedata                                      (cpu_data_master_writedata),
      .cpu_instruction_master_address_to_slave                        (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_granted_cpu_jtag_debug_module           (cpu_instruction_master_granted_cpu_jtag_debug_module),
      .cpu_instruction_master_latency_counter                         (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_cpu_jtag_debug_module (cpu_instruction_master_qualified_request_cpu_jtag_debug_module),
      .cpu_instruction_master_read                                    (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_cpu_jtag_debug_module   (cpu_instruction_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_instruction_master_requests_cpu_jtag_debug_module          (cpu_instruction_master_requests_cpu_jtag_debug_module),
      .cpu_jtag_debug_module_address                                  (cpu_jtag_debug_module_address),
      .cpu_jtag_debug_module_begintransfer                            (cpu_jtag_debug_module_begintransfer),
      .cpu_jtag_debug_module_byteenable                               (cpu_jtag_debug_module_byteenable),
      .cpu_jtag_debug_module_chipselect                               (cpu_jtag_debug_module_chipselect),
      .cpu_jtag_debug_module_debugaccess                              (cpu_jtag_debug_module_debugaccess),
      .cpu_jtag_debug_module_readdata                                 (cpu_jtag_debug_module_readdata),
      .cpu_jtag_debug_module_readdata_from_sa                         (cpu_jtag_debug_module_readdata_from_sa),
      .cpu_jtag_debug_module_reset                                    (cpu_jtag_debug_module_reset),
      .cpu_jtag_debug_module_reset_n                                  (cpu_jtag_debug_module_reset_n),
      .cpu_jtag_debug_module_resetrequest                             (cpu_jtag_debug_module_resetrequest),
      .cpu_jtag_debug_module_resetrequest_from_sa                     (cpu_jtag_debug_module_resetrequest_from_sa),
      .cpu_jtag_debug_module_write                                    (cpu_jtag_debug_module_write),
      .cpu_jtag_debug_module_writedata                                (cpu_jtag_debug_module_writedata),
      .d1_cpu_jtag_debug_module_end_xfer                              (d1_cpu_jtag_debug_module_end_xfer),
      .reset_n                                                        (clk_reset_n)
    );

  cpu_data_master_arbitrator the_cpu_data_master
    (
      .Din_s1_readdata_from_sa                                             (Din_s1_readdata_from_sa),
      .character_lcd_0_avalon_lcd_slave_readdata_from_sa                   (character_lcd_0_avalon_lcd_slave_readdata_from_sa),
      .character_lcd_0_avalon_lcd_slave_waitrequest_from_sa                (character_lcd_0_avalon_lcd_slave_waitrequest_from_sa),
      .clk                                                                 (clk),
      .cpu_data_master_address                                             (cpu_data_master_address),
      .cpu_data_master_address_to_slave                                    (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable_flash_s1                                 (cpu_data_master_byteenable_flash_s1),
      .cpu_data_master_byteenable_sram_0_avalon_sram_slave                 (cpu_data_master_byteenable_sram_0_avalon_sram_slave),
      .cpu_data_master_dbs_address                                         (cpu_data_master_dbs_address),
      .cpu_data_master_dbs_write_16                                        (cpu_data_master_dbs_write_16),
      .cpu_data_master_dbs_write_8                                         (cpu_data_master_dbs_write_8),
      .cpu_data_master_debugaccess                                         (cpu_data_master_debugaccess),
      .cpu_data_master_granted_Din_s1                                      (cpu_data_master_granted_Din_s1),
      .cpu_data_master_granted_Dout_s1                                     (cpu_data_master_granted_Dout_s1),
      .cpu_data_master_granted_SEG_H_s1                                    (cpu_data_master_granted_SEG_H_s1),
      .cpu_data_master_granted_SEG_l_s1                                    (cpu_data_master_granted_SEG_l_s1),
      .cpu_data_master_granted_addr_s1                                     (cpu_data_master_granted_addr_s1),
      .cpu_data_master_granted_character_lcd_0_avalon_lcd_slave            (cpu_data_master_granted_character_lcd_0_avalon_lcd_slave),
      .cpu_data_master_granted_cpu_jtag_debug_module                       (cpu_data_master_granted_cpu_jtag_debug_module),
      .cpu_data_master_granted_flash_s1                                    (cpu_data_master_granted_flash_s1),
      .cpu_data_master_granted_jtag_uart_avalon_jtag_slave                 (cpu_data_master_granted_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_granted_nCS_s1                                      (cpu_data_master_granted_nCS_s1),
      .cpu_data_master_granted_nRD_s1                                      (cpu_data_master_granted_nRD_s1),
      .cpu_data_master_granted_nWR_s1                                      (cpu_data_master_granted_nWR_s1),
      .cpu_data_master_granted_ps2_0_avalon_PS2_slave                      (cpu_data_master_granted_ps2_0_avalon_PS2_slave),
      .cpu_data_master_granted_sram_0_avalon_sram_slave                    (cpu_data_master_granted_sram_0_avalon_sram_slave),
      .cpu_data_master_granted_sysid_control_slave                         (cpu_data_master_granted_sysid_control_slave),
      .cpu_data_master_granted_timer_s1                                    (cpu_data_master_granted_timer_s1),
      .cpu_data_master_irq                                                 (cpu_data_master_irq),
      .cpu_data_master_no_byte_enables_and_last_term                       (cpu_data_master_no_byte_enables_and_last_term),
      .cpu_data_master_qualified_request_Din_s1                            (cpu_data_master_qualified_request_Din_s1),
      .cpu_data_master_qualified_request_Dout_s1                           (cpu_data_master_qualified_request_Dout_s1),
      .cpu_data_master_qualified_request_SEG_H_s1                          (cpu_data_master_qualified_request_SEG_H_s1),
      .cpu_data_master_qualified_request_SEG_l_s1                          (cpu_data_master_qualified_request_SEG_l_s1),
      .cpu_data_master_qualified_request_addr_s1                           (cpu_data_master_qualified_request_addr_s1),
      .cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave  (cpu_data_master_qualified_request_character_lcd_0_avalon_lcd_slave),
      .cpu_data_master_qualified_request_cpu_jtag_debug_module             (cpu_data_master_qualified_request_cpu_jtag_debug_module),
      .cpu_data_master_qualified_request_flash_s1                          (cpu_data_master_qualified_request_flash_s1),
      .cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave       (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_qualified_request_nCS_s1                            (cpu_data_master_qualified_request_nCS_s1),
      .cpu_data_master_qualified_request_nRD_s1                            (cpu_data_master_qualified_request_nRD_s1),
      .cpu_data_master_qualified_request_nWR_s1                            (cpu_data_master_qualified_request_nWR_s1),
      .cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave            (cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave),
      .cpu_data_master_qualified_request_sram_0_avalon_sram_slave          (cpu_data_master_qualified_request_sram_0_avalon_sram_slave),
      .cpu_data_master_qualified_request_sysid_control_slave               (cpu_data_master_qualified_request_sysid_control_slave),
      .cpu_data_master_qualified_request_timer_s1                          (cpu_data_master_qualified_request_timer_s1),
      .cpu_data_master_read                                                (cpu_data_master_read),
      .cpu_data_master_read_data_valid_Din_s1                              (cpu_data_master_read_data_valid_Din_s1),
      .cpu_data_master_read_data_valid_Dout_s1                             (cpu_data_master_read_data_valid_Dout_s1),
      .cpu_data_master_read_data_valid_SEG_H_s1                            (cpu_data_master_read_data_valid_SEG_H_s1),
      .cpu_data_master_read_data_valid_SEG_l_s1                            (cpu_data_master_read_data_valid_SEG_l_s1),
      .cpu_data_master_read_data_valid_addr_s1                             (cpu_data_master_read_data_valid_addr_s1),
      .cpu_data_master_read_data_valid_character_lcd_0_avalon_lcd_slave    (cpu_data_master_read_data_valid_character_lcd_0_avalon_lcd_slave),
      .cpu_data_master_read_data_valid_cpu_jtag_debug_module               (cpu_data_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_data_master_read_data_valid_flash_s1                            (cpu_data_master_read_data_valid_flash_s1),
      .cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave         (cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_read_data_valid_nCS_s1                              (cpu_data_master_read_data_valid_nCS_s1),
      .cpu_data_master_read_data_valid_nRD_s1                              (cpu_data_master_read_data_valid_nRD_s1),
      .cpu_data_master_read_data_valid_nWR_s1                              (cpu_data_master_read_data_valid_nWR_s1),
      .cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave              (cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave),
      .cpu_data_master_read_data_valid_sram_0_avalon_sram_slave            (cpu_data_master_read_data_valid_sram_0_avalon_sram_slave),
      .cpu_data_master_read_data_valid_sysid_control_slave                 (cpu_data_master_read_data_valid_sysid_control_slave),
      .cpu_data_master_read_data_valid_timer_s1                            (cpu_data_master_read_data_valid_timer_s1),
      .cpu_data_master_readdata                                            (cpu_data_master_readdata),
      .cpu_data_master_requests_Din_s1                                     (cpu_data_master_requests_Din_s1),
      .cpu_data_master_requests_Dout_s1                                    (cpu_data_master_requests_Dout_s1),
      .cpu_data_master_requests_SEG_H_s1                                   (cpu_data_master_requests_SEG_H_s1),
      .cpu_data_master_requests_SEG_l_s1                                   (cpu_data_master_requests_SEG_l_s1),
      .cpu_data_master_requests_addr_s1                                    (cpu_data_master_requests_addr_s1),
      .cpu_data_master_requests_character_lcd_0_avalon_lcd_slave           (cpu_data_master_requests_character_lcd_0_avalon_lcd_slave),
      .cpu_data_master_requests_cpu_jtag_debug_module                      (cpu_data_master_requests_cpu_jtag_debug_module),
      .cpu_data_master_requests_flash_s1                                   (cpu_data_master_requests_flash_s1),
      .cpu_data_master_requests_jtag_uart_avalon_jtag_slave                (cpu_data_master_requests_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_requests_nCS_s1                                     (cpu_data_master_requests_nCS_s1),
      .cpu_data_master_requests_nRD_s1                                     (cpu_data_master_requests_nRD_s1),
      .cpu_data_master_requests_nWR_s1                                     (cpu_data_master_requests_nWR_s1),
      .cpu_data_master_requests_ps2_0_avalon_PS2_slave                     (cpu_data_master_requests_ps2_0_avalon_PS2_slave),
      .cpu_data_master_requests_sram_0_avalon_sram_slave                   (cpu_data_master_requests_sram_0_avalon_sram_slave),
      .cpu_data_master_requests_sysid_control_slave                        (cpu_data_master_requests_sysid_control_slave),
      .cpu_data_master_requests_timer_s1                                   (cpu_data_master_requests_timer_s1),
      .cpu_data_master_waitrequest                                         (cpu_data_master_waitrequest),
      .cpu_data_master_write                                               (cpu_data_master_write),
      .cpu_data_master_writedata                                           (cpu_data_master_writedata),
      .cpu_jtag_debug_module_readdata_from_sa                              (cpu_jtag_debug_module_readdata_from_sa),
      .d1_Din_s1_end_xfer                                                  (d1_Din_s1_end_xfer),
      .d1_Dout_s1_end_xfer                                                 (d1_Dout_s1_end_xfer),
      .d1_SEG_H_s1_end_xfer                                                (d1_SEG_H_s1_end_xfer),
      .d1_SEG_l_s1_end_xfer                                                (d1_SEG_l_s1_end_xfer),
      .d1_addr_s1_end_xfer                                                 (d1_addr_s1_end_xfer),
      .d1_character_lcd_0_avalon_lcd_slave_end_xfer                        (d1_character_lcd_0_avalon_lcd_slave_end_xfer),
      .d1_cpu_jtag_debug_module_end_xfer                                   (d1_cpu_jtag_debug_module_end_xfer),
      .d1_jtag_uart_avalon_jtag_slave_end_xfer                             (d1_jtag_uart_avalon_jtag_slave_end_xfer),
      .d1_nCS_s1_end_xfer                                                  (d1_nCS_s1_end_xfer),
      .d1_nRD_s1_end_xfer                                                  (d1_nRD_s1_end_xfer),
      .d1_nWR_s1_end_xfer                                                  (d1_nWR_s1_end_xfer),
      .d1_ps2_0_avalon_PS2_slave_end_xfer                                  (d1_ps2_0_avalon_PS2_slave_end_xfer),
      .d1_sram_0_avalon_sram_slave_end_xfer                                (d1_sram_0_avalon_sram_slave_end_xfer),
      .d1_sysid_control_slave_end_xfer                                     (d1_sysid_control_slave_end_xfer),
      .d1_timer_s1_end_xfer                                                (d1_timer_s1_end_xfer),
      .d1_tristate_bridge_avalon_slave_end_xfer                            (d1_tristate_bridge_avalon_slave_end_xfer),
      .incoming_data_to_and_from_the_flash_with_Xs_converted_to_0          (incoming_data_to_and_from_the_flash_with_Xs_converted_to_0),
      .jtag_uart_avalon_jtag_slave_irq_from_sa                             (jtag_uart_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_avalon_jtag_slave_readdata_from_sa                        (jtag_uart_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_avalon_jtag_slave_waitrequest_from_sa                     (jtag_uart_avalon_jtag_slave_waitrequest_from_sa),
      .ps2_0_avalon_PS2_slave_irq_from_sa                                  (ps2_0_avalon_PS2_slave_irq_from_sa),
      .ps2_0_avalon_PS2_slave_readdata_from_sa                             (ps2_0_avalon_PS2_slave_readdata_from_sa),
      .ps2_0_avalon_PS2_slave_waitrequest_from_sa                          (ps2_0_avalon_PS2_slave_waitrequest_from_sa),
      .registered_cpu_data_master_read_data_valid_flash_s1                 (registered_cpu_data_master_read_data_valid_flash_s1),
      .registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave   (registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave),
      .registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave (registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave),
      .reset_n                                                             (clk_reset_n),
      .sram_0_avalon_sram_slave_readdata_from_sa                           (sram_0_avalon_sram_slave_readdata_from_sa),
      .sysid_control_slave_readdata_from_sa                                (sysid_control_slave_readdata_from_sa),
      .timer_s1_irq_from_sa                                                (timer_s1_irq_from_sa),
      .timer_s1_readdata_from_sa                                           (timer_s1_readdata_from_sa)
    );

  cpu_instruction_master_arbitrator the_cpu_instruction_master
    (
      .clk                                                               (clk),
      .cpu_instruction_master_address                                    (cpu_instruction_master_address),
      .cpu_instruction_master_address_to_slave                           (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_dbs_address                                (cpu_instruction_master_dbs_address),
      .cpu_instruction_master_granted_cpu_jtag_debug_module              (cpu_instruction_master_granted_cpu_jtag_debug_module),
      .cpu_instruction_master_granted_flash_s1                           (cpu_instruction_master_granted_flash_s1),
      .cpu_instruction_master_granted_sram_0_avalon_sram_slave           (cpu_instruction_master_granted_sram_0_avalon_sram_slave),
      .cpu_instruction_master_latency_counter                            (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_cpu_jtag_debug_module    (cpu_instruction_master_qualified_request_cpu_jtag_debug_module),
      .cpu_instruction_master_qualified_request_flash_s1                 (cpu_instruction_master_qualified_request_flash_s1),
      .cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave (cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave),
      .cpu_instruction_master_read                                       (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_cpu_jtag_debug_module      (cpu_instruction_master_read_data_valid_cpu_jtag_debug_module),
      .cpu_instruction_master_read_data_valid_flash_s1                   (cpu_instruction_master_read_data_valid_flash_s1),
      .cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave   (cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave),
      .cpu_instruction_master_readdata                                   (cpu_instruction_master_readdata),
      .cpu_instruction_master_readdatavalid                              (cpu_instruction_master_readdatavalid),
      .cpu_instruction_master_requests_cpu_jtag_debug_module             (cpu_instruction_master_requests_cpu_jtag_debug_module),
      .cpu_instruction_master_requests_flash_s1                          (cpu_instruction_master_requests_flash_s1),
      .cpu_instruction_master_requests_sram_0_avalon_sram_slave          (cpu_instruction_master_requests_sram_0_avalon_sram_slave),
      .cpu_instruction_master_waitrequest                                (cpu_instruction_master_waitrequest),
      .cpu_jtag_debug_module_readdata_from_sa                            (cpu_jtag_debug_module_readdata_from_sa),
      .d1_cpu_jtag_debug_module_end_xfer                                 (d1_cpu_jtag_debug_module_end_xfer),
      .d1_sram_0_avalon_sram_slave_end_xfer                              (d1_sram_0_avalon_sram_slave_end_xfer),
      .d1_tristate_bridge_avalon_slave_end_xfer                          (d1_tristate_bridge_avalon_slave_end_xfer),
      .incoming_data_to_and_from_the_flash                               (incoming_data_to_and_from_the_flash),
      .reset_n                                                           (clk_reset_n),
      .sram_0_avalon_sram_slave_readdata_from_sa                         (sram_0_avalon_sram_slave_readdata_from_sa)
    );

  cpu the_cpu
    (
      .clk                                   (clk),
      .d_address                             (cpu_data_master_address),
      .d_byteenable                          (cpu_data_master_byteenable),
      .d_irq                                 (cpu_data_master_irq),
      .d_read                                (cpu_data_master_read),
      .d_readdata                            (cpu_data_master_readdata),
      .d_waitrequest                         (cpu_data_master_waitrequest),
      .d_write                               (cpu_data_master_write),
      .d_writedata                           (cpu_data_master_writedata),
      .i_address                             (cpu_instruction_master_address),
      .i_read                                (cpu_instruction_master_read),
      .i_readdata                            (cpu_instruction_master_readdata),
      .i_readdatavalid                       (cpu_instruction_master_readdatavalid),
      .i_waitrequest                         (cpu_instruction_master_waitrequest),
      .jtag_debug_module_address             (cpu_jtag_debug_module_address),
      .jtag_debug_module_begintransfer       (cpu_jtag_debug_module_begintransfer),
      .jtag_debug_module_byteenable          (cpu_jtag_debug_module_byteenable),
      .jtag_debug_module_clk                 (clk),
      .jtag_debug_module_debugaccess         (cpu_jtag_debug_module_debugaccess),
      .jtag_debug_module_debugaccess_to_roms (cpu_data_master_debugaccess),
      .jtag_debug_module_readdata            (cpu_jtag_debug_module_readdata),
      .jtag_debug_module_reset               (cpu_jtag_debug_module_reset),
      .jtag_debug_module_resetrequest        (cpu_jtag_debug_module_resetrequest),
      .jtag_debug_module_select              (cpu_jtag_debug_module_chipselect),
      .jtag_debug_module_write               (cpu_jtag_debug_module_write),
      .jtag_debug_module_writedata           (cpu_jtag_debug_module_writedata),
      .reset_n                               (cpu_jtag_debug_module_reset_n)
    );

  jtag_uart_avalon_jtag_slave_arbitrator the_jtag_uart_avalon_jtag_slave
    (
      .clk                                                           (clk),
      .cpu_data_master_address_to_slave                              (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_jtag_uart_avalon_jtag_slave           (cpu_data_master_granted_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave (cpu_data_master_qualified_request_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_read                                          (cpu_data_master_read),
      .cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave   (cpu_data_master_read_data_valid_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_requests_jtag_uart_avalon_jtag_slave          (cpu_data_master_requests_jtag_uart_avalon_jtag_slave),
      .cpu_data_master_waitrequest                                   (cpu_data_master_waitrequest),
      .cpu_data_master_write                                         (cpu_data_master_write),
      .cpu_data_master_writedata                                     (cpu_data_master_writedata),
      .d1_jtag_uart_avalon_jtag_slave_end_xfer                       (d1_jtag_uart_avalon_jtag_slave_end_xfer),
      .jtag_uart_avalon_jtag_slave_address                           (jtag_uart_avalon_jtag_slave_address),
      .jtag_uart_avalon_jtag_slave_chipselect                        (jtag_uart_avalon_jtag_slave_chipselect),
      .jtag_uart_avalon_jtag_slave_dataavailable                     (jtag_uart_avalon_jtag_slave_dataavailable),
      .jtag_uart_avalon_jtag_slave_dataavailable_from_sa             (jtag_uart_avalon_jtag_slave_dataavailable_from_sa),
      .jtag_uart_avalon_jtag_slave_irq                               (jtag_uart_avalon_jtag_slave_irq),
      .jtag_uart_avalon_jtag_slave_irq_from_sa                       (jtag_uart_avalon_jtag_slave_irq_from_sa),
      .jtag_uart_avalon_jtag_slave_read_n                            (jtag_uart_avalon_jtag_slave_read_n),
      .jtag_uart_avalon_jtag_slave_readdata                          (jtag_uart_avalon_jtag_slave_readdata),
      .jtag_uart_avalon_jtag_slave_readdata_from_sa                  (jtag_uart_avalon_jtag_slave_readdata_from_sa),
      .jtag_uart_avalon_jtag_slave_readyfordata                      (jtag_uart_avalon_jtag_slave_readyfordata),
      .jtag_uart_avalon_jtag_slave_readyfordata_from_sa              (jtag_uart_avalon_jtag_slave_readyfordata_from_sa),
      .jtag_uart_avalon_jtag_slave_reset_n                           (jtag_uart_avalon_jtag_slave_reset_n),
      .jtag_uart_avalon_jtag_slave_waitrequest                       (jtag_uart_avalon_jtag_slave_waitrequest),
      .jtag_uart_avalon_jtag_slave_waitrequest_from_sa               (jtag_uart_avalon_jtag_slave_waitrequest_from_sa),
      .jtag_uart_avalon_jtag_slave_write_n                           (jtag_uart_avalon_jtag_slave_write_n),
      .jtag_uart_avalon_jtag_slave_writedata                         (jtag_uart_avalon_jtag_slave_writedata),
      .reset_n                                                       (clk_reset_n)
    );

  jtag_uart the_jtag_uart
    (
      .av_address     (jtag_uart_avalon_jtag_slave_address),
      .av_chipselect  (jtag_uart_avalon_jtag_slave_chipselect),
      .av_irq         (jtag_uart_avalon_jtag_slave_irq),
      .av_read_n      (jtag_uart_avalon_jtag_slave_read_n),
      .av_readdata    (jtag_uart_avalon_jtag_slave_readdata),
      .av_waitrequest (jtag_uart_avalon_jtag_slave_waitrequest),
      .av_write_n     (jtag_uart_avalon_jtag_slave_write_n),
      .av_writedata   (jtag_uart_avalon_jtag_slave_writedata),
      .clk            (clk),
      .dataavailable  (jtag_uart_avalon_jtag_slave_dataavailable),
      .readyfordata   (jtag_uart_avalon_jtag_slave_readyfordata),
      .rst_n          (jtag_uart_avalon_jtag_slave_reset_n)
    );

  nCS_s1_arbitrator the_nCS_s1
    (
      .clk                                      (clk),
      .cpu_data_master_address_to_slave         (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_nCS_s1           (cpu_data_master_granted_nCS_s1),
      .cpu_data_master_qualified_request_nCS_s1 (cpu_data_master_qualified_request_nCS_s1),
      .cpu_data_master_read                     (cpu_data_master_read),
      .cpu_data_master_read_data_valid_nCS_s1   (cpu_data_master_read_data_valid_nCS_s1),
      .cpu_data_master_requests_nCS_s1          (cpu_data_master_requests_nCS_s1),
      .cpu_data_master_waitrequest              (cpu_data_master_waitrequest),
      .cpu_data_master_write                    (cpu_data_master_write),
      .cpu_data_master_writedata                (cpu_data_master_writedata),
      .d1_nCS_s1_end_xfer                       (d1_nCS_s1_end_xfer),
      .nCS_s1_address                           (nCS_s1_address),
      .nCS_s1_chipselect                        (nCS_s1_chipselect),
      .nCS_s1_reset_n                           (nCS_s1_reset_n),
      .nCS_s1_write_n                           (nCS_s1_write_n),
      .nCS_s1_writedata                         (nCS_s1_writedata),
      .reset_n                                  (clk_reset_n)
    );

  nCS the_nCS
    (
      .address    (nCS_s1_address),
      .chipselect (nCS_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_nCS),
      .reset_n    (nCS_s1_reset_n),
      .write_n    (nCS_s1_write_n),
      .writedata  (nCS_s1_writedata)
    );

  nRD_s1_arbitrator the_nRD_s1
    (
      .clk                                      (clk),
      .cpu_data_master_address_to_slave         (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_nRD_s1           (cpu_data_master_granted_nRD_s1),
      .cpu_data_master_qualified_request_nRD_s1 (cpu_data_master_qualified_request_nRD_s1),
      .cpu_data_master_read                     (cpu_data_master_read),
      .cpu_data_master_read_data_valid_nRD_s1   (cpu_data_master_read_data_valid_nRD_s1),
      .cpu_data_master_requests_nRD_s1          (cpu_data_master_requests_nRD_s1),
      .cpu_data_master_waitrequest              (cpu_data_master_waitrequest),
      .cpu_data_master_write                    (cpu_data_master_write),
      .cpu_data_master_writedata                (cpu_data_master_writedata),
      .d1_nRD_s1_end_xfer                       (d1_nRD_s1_end_xfer),
      .nRD_s1_address                           (nRD_s1_address),
      .nRD_s1_chipselect                        (nRD_s1_chipselect),
      .nRD_s1_reset_n                           (nRD_s1_reset_n),
      .nRD_s1_write_n                           (nRD_s1_write_n),
      .nRD_s1_writedata                         (nRD_s1_writedata),
      .reset_n                                  (clk_reset_n)
    );

  nRD the_nRD
    (
      .address    (nRD_s1_address),
      .chipselect (nRD_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_nRD),
      .reset_n    (nRD_s1_reset_n),
      .write_n    (nRD_s1_write_n),
      .writedata  (nRD_s1_writedata)
    );

  nWR_s1_arbitrator the_nWR_s1
    (
      .clk                                      (clk),
      .cpu_data_master_address_to_slave         (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_nWR_s1           (cpu_data_master_granted_nWR_s1),
      .cpu_data_master_qualified_request_nWR_s1 (cpu_data_master_qualified_request_nWR_s1),
      .cpu_data_master_read                     (cpu_data_master_read),
      .cpu_data_master_read_data_valid_nWR_s1   (cpu_data_master_read_data_valid_nWR_s1),
      .cpu_data_master_requests_nWR_s1          (cpu_data_master_requests_nWR_s1),
      .cpu_data_master_waitrequest              (cpu_data_master_waitrequest),
      .cpu_data_master_write                    (cpu_data_master_write),
      .cpu_data_master_writedata                (cpu_data_master_writedata),
      .d1_nWR_s1_end_xfer                       (d1_nWR_s1_end_xfer),
      .nWR_s1_address                           (nWR_s1_address),
      .nWR_s1_chipselect                        (nWR_s1_chipselect),
      .nWR_s1_reset_n                           (nWR_s1_reset_n),
      .nWR_s1_write_n                           (nWR_s1_write_n),
      .nWR_s1_writedata                         (nWR_s1_writedata),
      .reset_n                                  (clk_reset_n)
    );

  nWR the_nWR
    (
      .address    (nWR_s1_address),
      .chipselect (nWR_s1_chipselect),
      .clk        (clk),
      .out_port   (out_port_from_the_nWR),
      .reset_n    (nWR_s1_reset_n),
      .write_n    (nWR_s1_write_n),
      .writedata  (nWR_s1_writedata)
    );

  ps2_0_avalon_PS2_slave_arbitrator the_ps2_0_avalon_PS2_slave
    (
      .clk                                                               (clk),
      .cpu_data_master_address_to_slave                                  (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                                        (cpu_data_master_byteenable),
      .cpu_data_master_granted_ps2_0_avalon_PS2_slave                    (cpu_data_master_granted_ps2_0_avalon_PS2_slave),
      .cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave          (cpu_data_master_qualified_request_ps2_0_avalon_PS2_slave),
      .cpu_data_master_read                                              (cpu_data_master_read),
      .cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave            (cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave),
      .cpu_data_master_requests_ps2_0_avalon_PS2_slave                   (cpu_data_master_requests_ps2_0_avalon_PS2_slave),
      .cpu_data_master_waitrequest                                       (cpu_data_master_waitrequest),
      .cpu_data_master_write                                             (cpu_data_master_write),
      .cpu_data_master_writedata                                         (cpu_data_master_writedata),
      .d1_ps2_0_avalon_PS2_slave_end_xfer                                (d1_ps2_0_avalon_PS2_slave_end_xfer),
      .ps2_0_avalon_PS2_slave_address                                    (ps2_0_avalon_PS2_slave_address),
      .ps2_0_avalon_PS2_slave_byteenable                                 (ps2_0_avalon_PS2_slave_byteenable),
      .ps2_0_avalon_PS2_slave_chipselect                                 (ps2_0_avalon_PS2_slave_chipselect),
      .ps2_0_avalon_PS2_slave_irq                                        (ps2_0_avalon_PS2_slave_irq),
      .ps2_0_avalon_PS2_slave_irq_from_sa                                (ps2_0_avalon_PS2_slave_irq_from_sa),
      .ps2_0_avalon_PS2_slave_read                                       (ps2_0_avalon_PS2_slave_read),
      .ps2_0_avalon_PS2_slave_readdata                                   (ps2_0_avalon_PS2_slave_readdata),
      .ps2_0_avalon_PS2_slave_readdata_from_sa                           (ps2_0_avalon_PS2_slave_readdata_from_sa),
      .ps2_0_avalon_PS2_slave_waitrequest                                (ps2_0_avalon_PS2_slave_waitrequest),
      .ps2_0_avalon_PS2_slave_waitrequest_from_sa                        (ps2_0_avalon_PS2_slave_waitrequest_from_sa),
      .ps2_0_avalon_PS2_slave_write                                      (ps2_0_avalon_PS2_slave_write),
      .ps2_0_avalon_PS2_slave_writedata                                  (ps2_0_avalon_PS2_slave_writedata),
      .registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave (registered_cpu_data_master_read_data_valid_ps2_0_avalon_PS2_slave),
      .reset_n                                                           (clk_reset_n)
    );

  ps2_0 the_ps2_0
    (
      .PS2_CLK     (PS2_CLK_to_and_from_the_ps2_0),
      .PS2_DAT     (PS2_DAT_to_and_from_the_ps2_0),
      .address     (ps2_0_avalon_PS2_slave_address),
      .byteenable  (ps2_0_avalon_PS2_slave_byteenable),
      .chipselect  (ps2_0_avalon_PS2_slave_chipselect),
      .clk         (clk),
      .irq         (ps2_0_avalon_PS2_slave_irq),
      .read        (ps2_0_avalon_PS2_slave_read),
      .readdata    (ps2_0_avalon_PS2_slave_readdata),
      .reset       (clk_reset),
      .waitrequest (ps2_0_avalon_PS2_slave_waitrequest),
      .write       (ps2_0_avalon_PS2_slave_write),
      .writedata   (ps2_0_avalon_PS2_slave_writedata)
    );

  sram_0_avalon_sram_slave_arbitrator the_sram_0_avalon_sram_slave
    (
      .clk                                                                 (clk),
      .cpu_data_master_address_to_slave                                    (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                                          (cpu_data_master_byteenable),
      .cpu_data_master_byteenable_sram_0_avalon_sram_slave                 (cpu_data_master_byteenable_sram_0_avalon_sram_slave),
      .cpu_data_master_dbs_address                                         (cpu_data_master_dbs_address),
      .cpu_data_master_dbs_write_16                                        (cpu_data_master_dbs_write_16),
      .cpu_data_master_granted_sram_0_avalon_sram_slave                    (cpu_data_master_granted_sram_0_avalon_sram_slave),
      .cpu_data_master_no_byte_enables_and_last_term                       (cpu_data_master_no_byte_enables_and_last_term),
      .cpu_data_master_qualified_request_sram_0_avalon_sram_slave          (cpu_data_master_qualified_request_sram_0_avalon_sram_slave),
      .cpu_data_master_read                                                (cpu_data_master_read),
      .cpu_data_master_read_data_valid_sram_0_avalon_sram_slave            (cpu_data_master_read_data_valid_sram_0_avalon_sram_slave),
      .cpu_data_master_requests_sram_0_avalon_sram_slave                   (cpu_data_master_requests_sram_0_avalon_sram_slave),
      .cpu_data_master_waitrequest                                         (cpu_data_master_waitrequest),
      .cpu_data_master_write                                               (cpu_data_master_write),
      .cpu_instruction_master_address_to_slave                             (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_dbs_address                                  (cpu_instruction_master_dbs_address),
      .cpu_instruction_master_granted_sram_0_avalon_sram_slave             (cpu_instruction_master_granted_sram_0_avalon_sram_slave),
      .cpu_instruction_master_latency_counter                              (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave   (cpu_instruction_master_qualified_request_sram_0_avalon_sram_slave),
      .cpu_instruction_master_read                                         (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave     (cpu_instruction_master_read_data_valid_sram_0_avalon_sram_slave),
      .cpu_instruction_master_requests_sram_0_avalon_sram_slave            (cpu_instruction_master_requests_sram_0_avalon_sram_slave),
      .d1_sram_0_avalon_sram_slave_end_xfer                                (d1_sram_0_avalon_sram_slave_end_xfer),
      .registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave (registered_cpu_data_master_read_data_valid_sram_0_avalon_sram_slave),
      .reset_n                                                             (clk_reset_n),
      .sram_0_avalon_sram_slave_address                                    (sram_0_avalon_sram_slave_address),
      .sram_0_avalon_sram_slave_byteenable                                 (sram_0_avalon_sram_slave_byteenable),
      .sram_0_avalon_sram_slave_chipselect                                 (sram_0_avalon_sram_slave_chipselect),
      .sram_0_avalon_sram_slave_read                                       (sram_0_avalon_sram_slave_read),
      .sram_0_avalon_sram_slave_readdata                                   (sram_0_avalon_sram_slave_readdata),
      .sram_0_avalon_sram_slave_readdata_from_sa                           (sram_0_avalon_sram_slave_readdata_from_sa),
      .sram_0_avalon_sram_slave_write                                      (sram_0_avalon_sram_slave_write),
      .sram_0_avalon_sram_slave_writedata                                  (sram_0_avalon_sram_slave_writedata)
    );

  sram_0 the_sram_0
    (
      .SRAM_ADDR  (SRAM_ADDR_from_the_sram_0),
      .SRAM_CE_N  (SRAM_CE_N_from_the_sram_0),
      .SRAM_DQ    (SRAM_DQ_to_and_from_the_sram_0),
      .SRAM_LB_N  (SRAM_LB_N_from_the_sram_0),
      .SRAM_OE_N  (SRAM_OE_N_from_the_sram_0),
      .SRAM_UB_N  (SRAM_UB_N_from_the_sram_0),
      .SRAM_WE_N  (SRAM_WE_N_from_the_sram_0),
      .address    (sram_0_avalon_sram_slave_address),
      .byteenable (sram_0_avalon_sram_slave_byteenable),
      .chipselect (sram_0_avalon_sram_slave_chipselect),
      .clk        (clk),
      .read       (sram_0_avalon_sram_slave_read),
      .readdata   (sram_0_avalon_sram_slave_readdata),
      .reset      (clk_reset),
      .write      (sram_0_avalon_sram_slave_write),
      .writedata  (sram_0_avalon_sram_slave_writedata)
    );

  sysid_control_slave_arbitrator the_sysid_control_slave
    (
      .clk                                                   (clk),
      .cpu_data_master_address_to_slave                      (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_sysid_control_slave           (cpu_data_master_granted_sysid_control_slave),
      .cpu_data_master_qualified_request_sysid_control_slave (cpu_data_master_qualified_request_sysid_control_slave),
      .cpu_data_master_read                                  (cpu_data_master_read),
      .cpu_data_master_read_data_valid_sysid_control_slave   (cpu_data_master_read_data_valid_sysid_control_slave),
      .cpu_data_master_requests_sysid_control_slave          (cpu_data_master_requests_sysid_control_slave),
      .cpu_data_master_write                                 (cpu_data_master_write),
      .d1_sysid_control_slave_end_xfer                       (d1_sysid_control_slave_end_xfer),
      .reset_n                                               (clk_reset_n),
      .sysid_control_slave_address                           (sysid_control_slave_address),
      .sysid_control_slave_readdata                          (sysid_control_slave_readdata),
      .sysid_control_slave_readdata_from_sa                  (sysid_control_slave_readdata_from_sa)
    );

  sysid the_sysid
    (
      .address  (sysid_control_slave_address),
      .readdata (sysid_control_slave_readdata)
    );

  timer_s1_arbitrator the_timer_s1
    (
      .clk                                        (clk),
      .cpu_data_master_address_to_slave           (cpu_data_master_address_to_slave),
      .cpu_data_master_granted_timer_s1           (cpu_data_master_granted_timer_s1),
      .cpu_data_master_qualified_request_timer_s1 (cpu_data_master_qualified_request_timer_s1),
      .cpu_data_master_read                       (cpu_data_master_read),
      .cpu_data_master_read_data_valid_timer_s1   (cpu_data_master_read_data_valid_timer_s1),
      .cpu_data_master_requests_timer_s1          (cpu_data_master_requests_timer_s1),
      .cpu_data_master_waitrequest                (cpu_data_master_waitrequest),
      .cpu_data_master_write                      (cpu_data_master_write),
      .cpu_data_master_writedata                  (cpu_data_master_writedata),
      .d1_timer_s1_end_xfer                       (d1_timer_s1_end_xfer),
      .reset_n                                    (clk_reset_n),
      .timer_s1_address                           (timer_s1_address),
      .timer_s1_chipselect                        (timer_s1_chipselect),
      .timer_s1_irq                               (timer_s1_irq),
      .timer_s1_irq_from_sa                       (timer_s1_irq_from_sa),
      .timer_s1_readdata                          (timer_s1_readdata),
      .timer_s1_readdata_from_sa                  (timer_s1_readdata_from_sa),
      .timer_s1_reset_n                           (timer_s1_reset_n),
      .timer_s1_write_n                           (timer_s1_write_n),
      .timer_s1_writedata                         (timer_s1_writedata)
    );

  timer the_timer
    (
      .address    (timer_s1_address),
      .chipselect (timer_s1_chipselect),
      .clk        (clk),
      .irq        (timer_s1_irq),
      .readdata   (timer_s1_readdata),
      .reset_n    (timer_s1_reset_n),
      .write_n    (timer_s1_write_n),
      .writedata  (timer_s1_writedata)
    );

  tristate_bridge_avalon_slave_arbitrator the_tristate_bridge_avalon_slave
    (
      .address_to_the_flash                                       (address_to_the_flash),
      .clk                                                        (clk),
      .cpu_data_master_address_to_slave                           (cpu_data_master_address_to_slave),
      .cpu_data_master_byteenable                                 (cpu_data_master_byteenable),
      .cpu_data_master_byteenable_flash_s1                        (cpu_data_master_byteenable_flash_s1),
      .cpu_data_master_dbs_address                                (cpu_data_master_dbs_address),
      .cpu_data_master_dbs_write_8                                (cpu_data_master_dbs_write_8),
      .cpu_data_master_granted_flash_s1                           (cpu_data_master_granted_flash_s1),
      .cpu_data_master_no_byte_enables_and_last_term              (cpu_data_master_no_byte_enables_and_last_term),
      .cpu_data_master_qualified_request_flash_s1                 (cpu_data_master_qualified_request_flash_s1),
      .cpu_data_master_read                                       (cpu_data_master_read),
      .cpu_data_master_read_data_valid_flash_s1                   (cpu_data_master_read_data_valid_flash_s1),
      .cpu_data_master_requests_flash_s1                          (cpu_data_master_requests_flash_s1),
      .cpu_data_master_waitrequest                                (cpu_data_master_waitrequest),
      .cpu_data_master_write                                      (cpu_data_master_write),
      .cpu_instruction_master_address_to_slave                    (cpu_instruction_master_address_to_slave),
      .cpu_instruction_master_dbs_address                         (cpu_instruction_master_dbs_address),
      .cpu_instruction_master_granted_flash_s1                    (cpu_instruction_master_granted_flash_s1),
      .cpu_instruction_master_latency_counter                     (cpu_instruction_master_latency_counter),
      .cpu_instruction_master_qualified_request_flash_s1          (cpu_instruction_master_qualified_request_flash_s1),
      .cpu_instruction_master_read                                (cpu_instruction_master_read),
      .cpu_instruction_master_read_data_valid_flash_s1            (cpu_instruction_master_read_data_valid_flash_s1),
      .cpu_instruction_master_requests_flash_s1                   (cpu_instruction_master_requests_flash_s1),
      .d1_tristate_bridge_avalon_slave_end_xfer                   (d1_tristate_bridge_avalon_slave_end_xfer),
      .data_to_and_from_the_flash                                 (data_to_and_from_the_flash),
      .incoming_data_to_and_from_the_flash                        (incoming_data_to_and_from_the_flash),
      .incoming_data_to_and_from_the_flash_with_Xs_converted_to_0 (incoming_data_to_and_from_the_flash_with_Xs_converted_to_0),
      .read_n_to_the_flash                                        (read_n_to_the_flash),
      .registered_cpu_data_master_read_data_valid_flash_s1        (registered_cpu_data_master_read_data_valid_flash_s1),
      .reset_n                                                    (clk_reset_n),
      .select_n_to_the_flash                                      (select_n_to_the_flash),
      .write_n_to_the_flash                                       (write_n_to_the_flash)
    );


endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module flash_lane0_module (
                            // inputs:
                             data,
                             rdaddress,
                             rdclken,
                             wraddress,
                             wrclock,
                             wren,

                            // outputs:
                             q
                          )
;

  output  [  7: 0] q;
  input   [  7: 0] data;
  input   [ 21: 0] rdaddress;
  input            rdclken;
  input   [ 21: 0] wraddress;
  input            wrclock;
  input            wren;

  reg     [  7: 0] mem_array [4194303: 0];
  wire    [  7: 0] q;
  reg     [ 21: 0] read_address;

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  always @(rdaddress)
    begin
      if (1)
          read_address <= rdaddress;
    end


  // Data read is asynchronous.
  assign q = mem_array[read_address];

initial
    $readmemh("flash.dat", mem_array);
  always @(posedge wrclock)
    begin
      // Write data
      if (wren)
          mem_array[wraddress] <= data;
    end



//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on
//synthesis read_comments_as_HDL on
//  always @(rdaddress)
//    begin
//      if (1)
//          read_address <= rdaddress;
//    end
//
//
//  lpm_ram_dp lpm_ram_dp_component
//    (
//      .data (data),
//      .q (q),
//      .rdaddress (read_address),
//      .rdclken (rdclken),
//      .wraddress (wraddress),
//      .wrclock (wrclock),
//      .wren (wren)
//    );
//
//  defparam lpm_ram_dp_component.lpm_file = "flash.mif",
//           lpm_ram_dp_component.lpm_hint = "USE_EAB=ON",
//           lpm_ram_dp_component.lpm_indata = "REGISTERED",
//           lpm_ram_dp_component.lpm_outdata = "UNREGISTERED",
//           lpm_ram_dp_component.lpm_rdaddress_control = "UNREGISTERED",
//           lpm_ram_dp_component.lpm_width = 8,
//           lpm_ram_dp_component.lpm_widthad = 22,
//           lpm_ram_dp_component.lpm_wraddress_control = "REGISTERED",
//           lpm_ram_dp_component.suppress_memory_conversion_warnings = "ON";
//
//synthesis read_comments_as_HDL off

endmodule



// turn off superfluous verilog processor warnings 
// altera message_level Level1 
// altera message_off 10034 10035 10036 10037 10230 10240 10030 

module flash (
               // inputs:
                address,
                read_n,
                select_n,
                write_n,

               // outputs:
                data
             )
;

  inout   [  7: 0] data;
  input   [ 21: 0] address;
  input            read_n;
  input            select_n;
  input            write_n;

  wire    [  7: 0] data;
  wire    [  7: 0] data_0;
  wire    [  7: 0] logic_vector_gasket;
  wire    [  7: 0] q_0;
  //s1, which is an e_ptf_slave

//synthesis translate_off
//////////////// SIMULATION-ONLY CONTENTS
  assign logic_vector_gasket = data;
  assign data_0 = logic_vector_gasket[7 : 0];
  //flash_lane0, which is an e_ram
  flash_lane0_module flash_lane0
    (
      .data      (data_0),
      .q         (q_0),
      .rdaddress (address),
      .rdclken   (1'b1),
      .wraddress (address),
      .wrclock   (write_n),
      .wren      (~select_n)
    );

  assign data = (~select_n & ~read_n)? q_0: {8{1'bz}};

//////////////// END SIMULATION-ONLY CONTENTS

//synthesis translate_on

endmodule


//synthesis translate_off



// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE

// AND HERE WILL BE PRESERVED </ALTERA_NOTE>


// If user logic components use Altsync_Ram with convert_hex2ver.dll,
// set USE_convert_hex2ver in the user comments section above

// `ifdef USE_convert_hex2ver
// `else
// `define NO_PLI 1
// `endif

`include "c:/altera/72/quartus/eda/sim_lib/altera_mf.v"
`include "c:/altera/72/quartus/eda/sim_lib/220model.v"
`include "c:/altera/72/quartus/eda/sim_lib/sgate.v"
`include "sysid.v"
`include "nWR.v"
`include "Din.v"
`include "timer.v"
`include "nRD.v"
`include "jtag_uart.v"
`include "SEG_l.v"
`include "Altera_UP_Avalon_PS2.v"
`include "Altera_UP_PS2.v"
`include "Altera_UP_PS2_Command_Out.v"
`include "Altera_UP_PS2_Data_In.v"
`include "ps2_0.v"
`include "SEG_H.v"
`include "cpu_test_bench.v"
`include "cpu_mult_cell.v"
`include "cpu_jtag_debug_module.v"
`include "cpu_jtag_debug_module_wrapper.v"
`include "cpu.v"
`include "nCS.v"
`include "Dout.v"
`include "addr.v"

`timescale 1ns / 1ps

module test_bench 
;


  wire             LCD_BLON_from_the_character_lcd_0;
  wire    [  7: 0] LCD_DATA_to_and_from_the_character_lcd_0;
  wire             LCD_EN_from_the_character_lcd_0;
  wire             LCD_ON_from_the_character_lcd_0;
  wire             LCD_RS_from_the_character_lcd_0;
  wire             LCD_RW_from_the_character_lcd_0;
  wire             PS2_CLK_to_and_from_the_ps2_0;
  wire             PS2_DAT_to_and_from_the_ps2_0;
  wire    [ 17: 0] SRAM_ADDR_from_the_sram_0;
  wire             SRAM_CE_N_from_the_sram_0;
  wire    [ 15: 0] SRAM_DQ_to_and_from_the_sram_0;
  wire             SRAM_LB_N_from_the_sram_0;
  wire             SRAM_OE_N_from_the_sram_0;
  wire             SRAM_UB_N_from_the_sram_0;
  wire             SRAM_WE_N_from_the_sram_0;
  wire    [ 21: 0] address_to_the_flash;
  reg              clk;
  wire    [  7: 0] data_to_and_from_the_flash;
  wire    [  7: 0] in_port_to_the_Din;
  wire             jtag_uart_avalon_jtag_slave_dataavailable_from_sa;
  wire             jtag_uart_avalon_jtag_slave_readyfordata_from_sa;
  wire    [  7: 0] out_port_from_the_Dout;
  wire    [  7: 0] out_port_from_the_SEG_H;
  wire    [  7: 0] out_port_from_the_SEG_l;
  wire    [  1: 0] out_port_from_the_addr;
  wire             out_port_from_the_nCS;
  wire             out_port_from_the_nRD;
  wire             out_port_from_the_nWR;
  wire             read_n_to_the_flash;
  reg              reset_n;
  wire             select_n_to_the_flash;
  wire             write_n_to_the_flash;


// <ALTERA_NOTE> CODE INSERTED BETWEEN HERE
//  add your signals and additional architecture here
// AND HERE WILL BE PRESERVED </ALTERA_NOTE>

  //Set us up the Dut
  testPro DUT
    (
      .LCD_BLON_from_the_character_lcd_0        (LCD_BLON_from_the_character_lcd_0),
      .LCD_DATA_to_and_from_the_character_lcd_0 (LCD_DATA_to_and_from_the_character_lcd_0),
      .LCD_EN_from_the_character_lcd_0          (LCD_EN_from_the_character_lcd_0),
      .LCD_ON_from_the_character_lcd_0          (LCD_ON_from_the_character_lcd_0),
      .LCD_RS_from_the_character_lcd_0          (LCD_RS_from_the_character_lcd_0),
      .LCD_RW_from_the_character_lcd_0          (LCD_RW_from_the_character_lcd_0),
      .PS2_CLK_to_and_from_the_ps2_0            (PS2_CLK_to_and_from_the_ps2_0),
      .PS2_DAT_to_and_from_the_ps2_0            (PS2_DAT_to_and_from_the_ps2_0),
      .SRAM_ADDR_from_the_sram_0                (SRAM_ADDR_from_the_sram_0),
      .SRAM_CE_N_from_the_sram_0                (SRAM_CE_N_from_the_sram_0),
      .SRAM_DQ_to_and_from_the_sram_0           (SRAM_DQ_to_and_from_the_sram_0),
      .SRAM_LB_N_from_the_sram_0                (SRAM_LB_N_from_the_sram_0),
      .SRAM_OE_N_from_the_sram_0                (SRAM_OE_N_from_the_sram_0),
      .SRAM_UB_N_from_the_sram_0                (SRAM_UB_N_from_the_sram_0),
      .SRAM_WE_N_from_the_sram_0                (SRAM_WE_N_from_the_sram_0),
      .address_to_the_flash                     (address_to_the_flash),
      .clk                                      (clk),
      .data_to_and_from_the_flash               (data_to_and_from_the_flash),
      .in_port_to_the_Din                       (in_port_to_the_Din),
      .out_port_from_the_Dout                   (out_port_from_the_Dout),
      .out_port_from_the_SEG_H                  (out_port_from_the_SEG_H),
      .out_port_from_the_SEG_l                  (out_port_from_the_SEG_l),
      .out_port_from_the_addr                   (out_port_from_the_addr),
      .out_port_from_the_nCS                    (out_port_from_the_nCS),
      .out_port_from_the_nRD                    (out_port_from_the_nRD),
      .out_port_from_the_nWR                    (out_port_from_the_nWR),
      .read_n_to_the_flash                      (read_n_to_the_flash),
      .reset_n                                  (reset_n),
      .select_n_to_the_flash                    (select_n_to_the_flash),
      .write_n_to_the_flash                     (write_n_to_the_flash)
    );

  flash the_flash
    (
      .address  (address_to_the_flash),
      .data     (data_to_and_from_the_flash),
      .read_n   (read_n_to_the_flash),
      .select_n (select_n_to_the_flash),
      .write_n  (write_n_to_the_flash)
    );

  initial
    clk = 1'b0;
  always
    #10 clk <= ~clk;
  
  initial 
    begin
      reset_n <= 0;
      #200 reset_n <= 1;
    end

endmodule


//synthesis translate_on